2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/device.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
23 #include <linux/irqchip/versatile-fpga.h>
24 #include <linux/gfp.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/platform_data/clk-integrator.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/sys_soc.h>
32 #include <mach/hardware.h>
33 #include <mach/platform.h>
34 #include <asm/setup.h>
35 #include <asm/mach-types.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/time.h>
46 #include <asm/hardware/timer-sp.h>
48 #include <plat/clcd.h>
49 #include <plat/sched_clock.h>
54 /* Base address to the CP controller */
55 static void __iomem *intcp_con_base;
57 #define INTCP_PA_FLASH_BASE 0x24000000
59 #define INTCP_PA_CLCD_BASE 0xc0000000
61 #define INTCP_FLASHPROG 0x04
62 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
63 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
67 * f1200000 12000000 EBI registers
68 * f1300000 13000000 Counter/Timer
69 * f1400000 14000000 Interrupt controller
70 * f1600000 16000000 UART 0
71 * f1700000 17000000 UART 1
72 * f1a00000 1a000000 Debug LEDs
73 * fc900000 c9000000 GPIO
74 * fca00000 ca000000 SIC
77 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
79 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
80 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
84 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
85 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
89 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
90 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
94 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
99 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
104 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
109 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
116 static void __init intcp_map_io(void)
118 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
124 static int intcp_flash_init(struct platform_device *dev)
128 val = readl(intcp_con_base + INTCP_FLASHPROG);
129 val |= CINTEGRATOR_FLASHPROG_FLWREN;
130 writel(val, intcp_con_base + INTCP_FLASHPROG);
135 static void intcp_flash_exit(struct platform_device *dev)
139 val = readl(intcp_con_base + INTCP_FLASHPROG);
140 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
141 writel(val, intcp_con_base + INTCP_FLASHPROG);
144 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
148 val = readl(intcp_con_base + INTCP_FLASHPROG);
150 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
152 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
153 writel(val, intcp_con_base + INTCP_FLASHPROG);
156 static struct physmap_flash_data intcp_flash_data = {
158 .init = intcp_flash_init,
159 .exit = intcp_flash_exit,
160 .set_vpp = intcp_flash_set_vpp,
164 * It seems that the card insertion interrupt remains active after
165 * we've acknowledged it. We therefore ignore the interrupt, and
166 * rely on reading it from the SIC. This also means that we must
167 * clear the latched interrupt.
169 static unsigned int mmc_status(struct device *dev)
171 unsigned int status = readl(__io_address(0xca000000 + 4));
172 writel(8, intcp_con_base + 8);
177 static struct mmci_platform_data mmc_data = {
178 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
179 .status = mmc_status,
188 * Ensure VGA is selected.
190 static void cp_clcd_enable(struct clcd_fb *fb)
192 struct fb_var_screeninfo *var = &fb->fb.var;
193 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
194 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
196 if (var->bits_per_pixel <= 8 ||
197 (var->bits_per_pixel == 16 && var->green.length == 5))
198 /* Pseudocolor, RGB555, BGR555 */
199 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
200 else if (fb->fb.var.bits_per_pixel <= 16)
201 /* truecolor RGB565 */
202 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
204 val = 0; /* no idea for this, don't trust the docs */
206 cm_control(CM_CTRL_LCDMUXSEL_MASK|
212 CM_CTRL_n24BITEN, val);
215 static int cp_clcd_setup(struct clcd_fb *fb)
217 fb->panel = versatile_clcd_get_panel("VGA");
221 return versatile_clcd_setup_dma(fb, SZ_1M);
224 static struct clcd_board clcd_data = {
225 .name = "Integrator/CP",
226 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
227 .check = clcdfb_check,
228 .decode = clcdfb_decode,
229 .enable = cp_clcd_enable,
230 .setup = cp_clcd_setup,
231 .mmap = versatile_clcd_mmap_dma,
232 .remove = versatile_clcd_remove_dma,
235 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
237 static void __init intcp_init_early(void)
239 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
240 versatile_sched_clock_init(REFCOUNTER, 24000000);
244 static const struct of_device_id fpga_irq_of_match[] __initconst = {
245 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
249 static void __init intcp_init_irq_of(void)
252 of_irq_init(fpga_irq_of_match);
253 integrator_clk_init(true);
257 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
258 * and enforce the bus names since these are used for clock lookups.
260 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
261 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
263 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
265 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
267 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
269 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
271 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
273 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
275 OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
277 OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
278 "physmap-flash", &intcp_flash_data),
282 static const struct of_device_id intcp_syscon_match[] = {
283 { .compatible = "arm,integrator-cp-syscon"},
287 static void __init intcp_init_of(void)
289 struct device_node *root;
290 struct device_node *cpcon;
291 struct device *parent;
292 struct soc_device *soc_dev;
293 struct soc_device_attribute *soc_dev_attr;
297 /* Here we create an SoC device for the root node */
298 root = of_find_node_by_path("/");
302 cpcon = of_find_matching_node(root, intcp_syscon_match);
306 intcp_con_base = of_iomap(cpcon, 0);
310 intcp_sc_id = readl(intcp_con_base);
312 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
316 err = of_property_read_string(root, "compatible",
317 &soc_dev_attr->soc_id);
320 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
323 soc_dev_attr->family = "Integrator";
324 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
325 'A' + (intcp_sc_id & 0x0f));
327 soc_dev = soc_device_register(soc_dev_attr);
328 if (IS_ERR(soc_dev)) {
329 kfree(soc_dev_attr->revision);
334 parent = soc_device_to_device(soc_dev);
335 integrator_init_sysfs(parent, intcp_sc_id);
336 of_platform_populate(root, of_default_bus_match_table,
337 intcp_auxdata_lookup, parent);
340 static const char * intcp_dt_board_compat[] = {
345 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
346 .reserve = integrator_reserve,
347 .map_io = intcp_map_io,
348 .init_early = intcp_init_early,
349 .init_irq = intcp_init_irq_of,
350 .handle_irq = fpga_handle_irq,
351 .init_machine = intcp_init_of,
352 .restart = integrator_restart,
353 .dt_compat = intcp_dt_board_compat,