arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/clk-integrator.h>
  37 #include <linux/of_irq.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_platform.h>
  40 #include <video/vga.h>
  41
  42 #include <mach/hardware.h>
  43 #include <mach/platform.h>
  44 #include <asm/hardware/arm_timer.h>
  45 #include <asm/setup.h>
  46 #include <asm/param.h>          /* HZ */
  47 #include <asm/mach-types.h>
  48 #include <asm/sched_clock.h>
  49
  50 #include <mach/lm.h>
  51 #include <mach/irqs.h>
  52
  53 #include <asm/mach/arch.h>
  54 #include <asm/mach/irq.h>
  55 #include <asm/mach/map.h>
  56 #include <asm/mach/time.h>
  57
  58 #include <plat/fpga-irq.h>
  59
  60 #include "common.h"
  61
  62 /*
  63  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  64  * is the (PA >> 12).
  65  *
  66  * Setup a VA for the Integrator interrupt controller (for header #0,
  67  * just for now).
  68  */
  69 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  70 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  71 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  72 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  73
  74 /*
  75  * Logical      Physical
  76  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  77  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  78  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  79  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  80  * ef000000                     Cache flush
  81  * f1000000     10000000        Core module registers
  82  * f1100000     11000000        System controller registers
  83  * f1200000     12000000        EBI registers
  84  * f1300000     13000000        Counter/Timer
  85  * f1400000     14000000        Interrupt controller
  86  * f1600000     16000000        UART 0
  87  * f1700000     17000000        UART 1
  88  * f1a00000     1a000000        Debug LEDs
  89  * f1b00000     1b000000        GPIO
  90  */
  91
  92 static struct map_desc ap_io_desc[] __initdata = {
  93         {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 105                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 110                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 115                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE
 118         }, {
 119                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 120                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE
 123         }, {
 124                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 125                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE
 128         }, {
 129                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 130                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE
 133         }, {
 134                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 135                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE
 138         }, {
 139                 .virtual        = PCI_MEMORY_VADDR,
 140                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 141                 .length         = SZ_16M,
 142                 .type           = MT_DEVICE
 143         }, {
 144                 .virtual        = PCI_CONFIG_VADDR,
 145                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 146                 .length         = SZ_16M,
 147                 .type           = MT_DEVICE
 148         }, {
 149                 .virtual        = PCI_V3_VADDR,
 150                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 151                 .length         = SZ_64K,
 152                 .type           = MT_DEVICE
 153         }, {
 154                 .virtual        = PCI_IO_VADDR,
 155                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 156                 .length         = SZ_64K,
 157                 .type           = MT_DEVICE
 158         }
 159 };
 160
 161 static void __init ap_map_io(void)
 162 {
 163         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 164         vga_base = PCI_MEMORY_VADDR;
 165 }
 166
 167 #ifdef CONFIG_PM
 168 static unsigned long ic_irq_enable;
 169
 170 static int irq_suspend(void)
 171 {
 172         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 173         return 0;
 174 }
 175
 176 static void irq_resume(void)
 177 {
 178         /* disable all irq sources */
 179         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 180         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 181         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 182
 183         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 184 }
 185 #else
 186 #define irq_suspend NULL
 187 #define irq_resume NULL
 188 #endif
 189
 190 static struct syscore_ops irq_syscore_ops = {
 191         .suspend        = irq_suspend,
 192         .resume         = irq_resume,
 193 };
 194
 195 static int __init irq_syscore_init(void)
 196 {
 197         register_syscore_ops(&irq_syscore_ops);
 198
 199         return 0;
 200 }
 201
 202 device_initcall(irq_syscore_init);
 203
 204 /*
 205  * Flash handling.
 206  */
 207 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 208 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 209 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 210 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 211
 212 static int ap_flash_init(struct platform_device *dev)
 213 {
 214         u32 tmp;
 215
 216         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 217
 218         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 219         writel(tmp, EBI_CSR1);
 220
 221         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 222                 writel(0xa05f, EBI_LOCK);
 223                 writel(tmp, EBI_CSR1);
 224                 writel(0, EBI_LOCK);
 225         }
 226         return 0;
 227 }
 228
 229 static void ap_flash_exit(struct platform_device *dev)
 230 {
 231         u32 tmp;
 232
 233         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 234
 235         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 236         writel(tmp, EBI_CSR1);
 237
 238         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 239                 writel(0xa05f, EBI_LOCK);
 240                 writel(tmp, EBI_CSR1);
 241                 writel(0, EBI_LOCK);
 242         }
 243 }
 244
 245 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 246 {
 247         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 248
 249         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 250 }
 251
 252 static struct physmap_flash_data ap_flash_data = {
 253         .width          = 4,
 254         .init           = ap_flash_init,
 255         .exit           = ap_flash_exit,
 256         .set_vpp        = ap_flash_set_vpp,
 257 };
 258
 259 /*
 260  * Where is the timer (VA)?
 261  */
 262 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 263 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 264 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 265
 266 static unsigned long timer_reload;
 267
 268 static u32 notrace integrator_read_sched_clock(void)
 269 {
 270         return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 271 }
 272
 273 static void integrator_clocksource_init(unsigned long inrate,
 274                                         void __iomem *base)
 275 {
 276         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 277         unsigned long rate = inrate;
 278
 279         if (rate >= 1500000) {
 280                 rate /= 16;
 281                 ctrl |= TIMER_CTRL_DIV16;
 282         }
 283
 284         writel(0xffff, base + TIMER_LOAD);
 285         writel(ctrl, base + TIMER_CTRL);
 286
 287         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 288                         rate, 200, 16, clocksource_mmio_readl_down);
 289         setup_sched_clock(integrator_read_sched_clock, 16, rate);
 290 }
 291
 292 static void __iomem * clkevt_base;
 293
 294 /*
 295  * IRQ handler for the timer
 296  */
 297 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 298 {
 299         struct clock_event_device *evt = dev_id;
 300
 301         /* clear the interrupt */
 302         writel(1, clkevt_base + TIMER_INTCLR);
 303
 304         evt->event_handler(evt);
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 310 {
 311         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 312
 313         /* Disable timer */
 314         writel(ctrl, clkevt_base + TIMER_CTRL);
 315
 316         switch (mode) {
 317         case CLOCK_EVT_MODE_PERIODIC:
 318                 /* Enable the timer and start the periodic tick */
 319                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 320                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 321                 writel(ctrl, clkevt_base + TIMER_CTRL);
 322                 break;
 323         case CLOCK_EVT_MODE_ONESHOT:
 324                 /* Leave the timer disabled, .set_next_event will enable it */
 325                 ctrl &= ~TIMER_CTRL_PERIODIC;
 326                 writel(ctrl, clkevt_base + TIMER_CTRL);
 327                 break;
 328         case CLOCK_EVT_MODE_UNUSED:
 329         case CLOCK_EVT_MODE_SHUTDOWN:
 330         case CLOCK_EVT_MODE_RESUME:
 331         default:
 332                 /* Just leave in disabled state */
 333                 break;
 334         }
 335
 336 }
 337
 338 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 339 {
 340         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 341
 342         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 343         writel(next, clkevt_base + TIMER_LOAD);
 344         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 345
 346         return 0;
 347 }
 348
 349 static struct clock_event_device integrator_clockevent = {
 350         .name           = "timer1",
 351         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 352         .set_mode       = clkevt_set_mode,
 353         .set_next_event = clkevt_set_next_event,
 354         .rating         = 300,
 355 };
 356
 357 static struct irqaction integrator_timer_irq = {
 358         .name           = "timer",
 359         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 360         .handler        = integrator_timer_interrupt,
 361         .dev_id         = &integrator_clockevent,
 362 };
 363
 364 static void integrator_clockevent_init(unsigned long inrate,
 365                                 void __iomem *base, int irq)
 366 {
 367         unsigned long rate = inrate;
 368         unsigned int ctrl = 0;
 369
 370         clkevt_base = base;
 371         /* Calculate and program a divisor */
 372         if (rate > 0x100000 * HZ) {
 373                 rate /= 256;
 374                 ctrl |= TIMER_CTRL_DIV256;
 375         } else if (rate > 0x10000 * HZ) {
 376                 rate /= 16;
 377                 ctrl |= TIMER_CTRL_DIV16;
 378         }
 379         timer_reload = rate / HZ;
 380         writel(ctrl, clkevt_base + TIMER_CTRL);
 381
 382         setup_irq(irq, &integrator_timer_irq);
 383         clockevents_config_and_register(&integrator_clockevent,
 384                                         rate,
 385                                         1,
 386                                         0xffffU);
 387 }
 388
 389 void __init ap_init_early(void)
 390 {
 391 }
 392
 393 #ifdef CONFIG_OF
 394
 395 static void __init ap_init_timer_of(void)
 396 {
 397         struct device_node *node;
 398         const char *path;
 399         void __iomem *base;
 400         int err;
 401         int irq;
 402         struct clk *clk;
 403         unsigned long rate;
 404
 405         clk = clk_get_sys("ap_timer", NULL);
 406         BUG_ON(IS_ERR(clk));
 407         clk_prepare_enable(clk);
 408         rate = clk_get_rate(clk);
 409
 410         err = of_property_read_string(of_aliases,
 411                                 "arm,timer-primary", &path);
 412         if (WARN_ON(err))
 413                 return;
 414         node = of_find_node_by_path(path);
 415         base = of_iomap(node, 0);
 416         if (WARN_ON(!base))
 417                 return;
 418         writel(0, base + TIMER_CTRL);
 419         integrator_clocksource_init(rate, base);
 420
 421         err = of_property_read_string(of_aliases,
 422                                 "arm,timer-secondary", &path);
 423         if (WARN_ON(err))
 424                 return;
 425         node = of_find_node_by_path(path);
 426         base = of_iomap(node, 0);
 427         if (WARN_ON(!base))
 428                 return;
 429         irq = irq_of_parse_and_map(node, 0);
 430         writel(0, base + TIMER_CTRL);
 431         integrator_clockevent_init(rate, base, irq);
 432 }
 433
 434 static struct sys_timer ap_of_timer = {
 435         .init           = ap_init_timer_of,
 436 };
 437
 438 static const struct of_device_id fpga_irq_of_match[] __initconst = {
 439         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
 440         { /* Sentinel */ }
 441 };
 442
 443 static void __init ap_init_irq_of(void)
 444 {
 445         /* disable core module IRQs */
 446         writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 447         of_irq_init(fpga_irq_of_match);
 448         integrator_clk_init(false);
 449 }
 450
 451 /* For the Device Tree, add in the UART callbacks as AUXDATA */
 452 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 453         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
 454                 "rtc", NULL),
 455         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 456                 "uart0", &integrator_uart_data),
 457         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 458                 "uart1", &integrator_uart_data),
 459         OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
 460                 "kmi0", NULL),
 461         OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 462                 "kmi1", NULL),
 463         OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
 464                 "physmap-flash", &ap_flash_data),
 465         { /* sentinel */ },
 466 };
 467
 468 static void __init ap_init_of(void)
 469 {
 470         unsigned long sc_dec;
 471         int i;
 472
 473         of_platform_populate(NULL, of_default_bus_match_table,
 474                         ap_auxdata_lookup, NULL);
 475
 476         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 477         for (i = 0; i < 4; i++) {
 478                 struct lm_device *lmdev;
 479
 480                 if ((sc_dec & (16 << i)) == 0)
 481                         continue;
 482
 483                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 484                 if (!lmdev)
 485                         continue;
 486
 487                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 488                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 489                 lmdev->resource.flags = IORESOURCE_MEM;
 490                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 491                 lmdev->id = i;
 492
 493                 lm_device_register(lmdev);
 494         }
 495 }
 496
 497 static const char * ap_dt_board_compat[] = {
 498         "arm,integrator-ap",
 499         NULL,
 500 };
 501
 502 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 503         .reserve        = integrator_reserve,
 504         .map_io         = ap_map_io,
 505         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 506         .init_early     = ap_init_early,
 507         .init_irq       = ap_init_irq_of,
 508         .handle_irq     = fpga_handle_irq,
 509         .timer          = &ap_of_timer,
 510         .init_machine   = ap_init_of,
 511         .restart        = integrator_restart,
 512         .dt_compat      = ap_dt_board_compat,
 513 MACHINE_END
 514
 515 #endif
 516
 517 #ifdef CONFIG_ATAGS
 518
 519 /*
 520  * This is where non-devicetree initialization code is collected and stashed
 521  * for eventual deletion.
 522  */
 523
 524 static struct resource cfi_flash_resource = {
 525         .start          = INTEGRATOR_FLASH_BASE,
 526         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 527         .flags          = IORESOURCE_MEM,
 528 };
 529
 530 static struct platform_device cfi_flash_device = {
 531         .name           = "physmap-flash",
 532         .id             = 0,
 533         .dev            = {
 534                 .platform_data  = &ap_flash_data,
 535         },
 536         .num_resources  = 1,
 537         .resource       = &cfi_flash_resource,
 538 };
 539
 540 static void __init ap_init_timer(void)
 541 {
 542         struct clk *clk;
 543         unsigned long rate;
 544
 545         clk = clk_get_sys("ap_timer", NULL);
 546         BUG_ON(IS_ERR(clk));
 547         clk_prepare_enable(clk);
 548         rate = clk_get_rate(clk);
 549
 550         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 551         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 552         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 553
 554         integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
 555         integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
 556                                 IRQ_TIMERINT1);
 557 }
 558
 559 static struct sys_timer ap_timer = {
 560         .init           = ap_init_timer,
 561 };
 562
 563 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 564
 565 static void __init ap_init_irq(void)
 566 {
 567         /* Disable all interrupts initially. */
 568         /* Do the core module ones */
 569         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 570
 571         /* do the header card stuff next */
 572         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 573         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 574
 575         fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
 576                 -1, INTEGRATOR_SC_VALID_INT, NULL);
 577         integrator_clk_init(false);
 578 }
 579
 580 static void __init ap_init(void)
 581 {
 582         unsigned long sc_dec;
 583         int i;
 584
 585         platform_device_register(&cfi_flash_device);
 586
 587         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 588         for (i = 0; i < 4; i++) {
 589                 struct lm_device *lmdev;
 590
 591                 if ((sc_dec & (16 << i)) == 0)
 592                         continue;
 593
 594                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 595                 if (!lmdev)
 596                         continue;
 597
 598                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 599                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 600                 lmdev->resource.flags = IORESOURCE_MEM;
 601                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 602                 lmdev->id = i;
 603
 604                 lm_device_register(lmdev);
 605         }
 606
 607         integrator_init(false);
 608 }
 609
 610 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 611         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 612         .atag_offset    = 0x100,
 613         .reserve        = integrator_reserve,
 614         .map_io         = ap_map_io,
 615         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
 616         .init_early     = ap_init_early,
 617         .init_irq       = ap_init_irq,
 618         .handle_irq     = fpga_handle_irq,
 619         .timer          = &ap_timer,
 620         .init_machine   = ap_init,
 621         .restart        = integrator_restart,
 622 MACHINE_END
 623
 624 #endif