2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
34 #include <linux/irqchip/versatile-fpga.h>
35 #include <linux/mtd/physmap.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/clk-integrator.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_address.h>
40 #include <linux/of_platform.h>
41 #include <linux/stat.h>
42 #include <linux/sys_soc.h>
43 #include <linux/termios.h>
45 #include <mach/hardware.h>
46 #include <mach/platform.h>
47 #include <asm/hardware/arm_timer.h>
48 #include <asm/setup.h>
49 #include <asm/param.h> /* HZ */
50 #include <asm/mach-types.h>
51 #include <asm/sched_clock.h>
54 #include <mach/irqs.h>
56 #include <asm/mach/arch.h>
57 #include <asm/mach/irq.h>
58 #include <asm/mach/map.h>
59 #include <asm/mach/pci.h>
60 #include <asm/mach/time.h>
64 /* Base address to the AP system controller */
65 void __iomem *ap_syscon_base;
68 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
71 * Setup a VA for the Integrator interrupt controller (for header #0,
74 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
75 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
76 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
80 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
81 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
82 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
83 * ef000000 Cache flush
84 * f1000000 10000000 Core module registers
85 * f1100000 11000000 System controller registers
86 * f1200000 12000000 EBI registers
87 * f1300000 13000000 Counter/Timer
88 * f1400000 14000000 Interrupt controller
89 * f1600000 16000000 UART 0
90 * f1700000 17000000 UART 1
91 * f1a00000 1a000000 Debug LEDs
92 * f1b00000 1b000000 GPIO
95 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
97 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
98 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
102 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
103 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
107 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
108 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
112 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
113 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
117 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
118 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
122 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
123 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
127 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
128 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
132 .virtual = (unsigned long)PCI_MEMORY_VADDR,
133 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
137 .virtual = (unsigned long)PCI_CONFIG_VADDR,
138 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
144 static void __init ap_map_io(void)
146 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
147 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
151 static unsigned long ic_irq_enable;
153 static int irq_suspend(void)
155 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
159 static void irq_resume(void)
161 /* disable all irq sources */
162 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
163 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
164 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
166 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
169 #define irq_suspend NULL
170 #define irq_resume NULL
173 static struct syscore_ops irq_syscore_ops = {
174 .suspend = irq_suspend,
175 .resume = irq_resume,
178 static int __init irq_syscore_init(void)
180 register_syscore_ops(&irq_syscore_ops);
185 device_initcall(irq_syscore_init);
190 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
191 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
193 static int ap_flash_init(struct platform_device *dev)
197 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
198 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
200 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
201 writel(tmp, EBI_CSR1);
203 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
204 writel(0xa05f, EBI_LOCK);
205 writel(tmp, EBI_CSR1);
211 static void ap_flash_exit(struct platform_device *dev)
215 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
216 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
218 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
219 writel(tmp, EBI_CSR1);
221 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
222 writel(0xa05f, EBI_LOCK);
223 writel(tmp, EBI_CSR1);
228 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
231 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
232 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
234 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
235 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
238 static struct physmap_flash_data ap_flash_data = {
240 .init = ap_flash_init,
241 .exit = ap_flash_exit,
242 .set_vpp = ap_flash_set_vpp,
246 * For the PL010 found in the Integrator/AP some of the UART control is
247 * implemented in the system controller and accessed using a callback
250 static void integrator_uart_set_mctrl(struct amba_device *dev,
251 void __iomem *base, unsigned int mctrl)
253 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
254 u32 phybase = dev->res.start;
256 if (phybase == INTEGRATOR_UART0_BASE) {
266 if (mctrl & TIOCM_RTS)
271 if (mctrl & TIOCM_DTR)
276 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
277 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
280 struct amba_pl010_data ap_uart_data = {
281 .set_mctrl = integrator_uart_set_mctrl,
285 * Where is the timer (VA)?
287 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
288 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
289 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
291 static unsigned long timer_reload;
293 static u32 notrace integrator_read_sched_clock(void)
295 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
298 static void integrator_clocksource_init(unsigned long inrate,
301 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
302 unsigned long rate = inrate;
304 if (rate >= 1500000) {
306 ctrl |= TIMER_CTRL_DIV16;
309 writel(0xffff, base + TIMER_LOAD);
310 writel(ctrl, base + TIMER_CTRL);
312 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
313 rate, 200, 16, clocksource_mmio_readl_down);
314 setup_sched_clock(integrator_read_sched_clock, 16, rate);
317 static void __iomem * clkevt_base;
320 * IRQ handler for the timer
322 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
324 struct clock_event_device *evt = dev_id;
326 /* clear the interrupt */
327 writel(1, clkevt_base + TIMER_INTCLR);
329 evt->event_handler(evt);
334 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
336 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
339 writel(ctrl, clkevt_base + TIMER_CTRL);
342 case CLOCK_EVT_MODE_PERIODIC:
343 /* Enable the timer and start the periodic tick */
344 writel(timer_reload, clkevt_base + TIMER_LOAD);
345 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
346 writel(ctrl, clkevt_base + TIMER_CTRL);
348 case CLOCK_EVT_MODE_ONESHOT:
349 /* Leave the timer disabled, .set_next_event will enable it */
350 ctrl &= ~TIMER_CTRL_PERIODIC;
351 writel(ctrl, clkevt_base + TIMER_CTRL);
353 case CLOCK_EVT_MODE_UNUSED:
354 case CLOCK_EVT_MODE_SHUTDOWN:
355 case CLOCK_EVT_MODE_RESUME:
357 /* Just leave in disabled state */
363 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
365 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
367 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
368 writel(next, clkevt_base + TIMER_LOAD);
369 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
374 static struct clock_event_device integrator_clockevent = {
376 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
377 .set_mode = clkevt_set_mode,
378 .set_next_event = clkevt_set_next_event,
382 static struct irqaction integrator_timer_irq = {
384 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
385 .handler = integrator_timer_interrupt,
386 .dev_id = &integrator_clockevent,
389 static void integrator_clockevent_init(unsigned long inrate,
390 void __iomem *base, int irq)
392 unsigned long rate = inrate;
393 unsigned int ctrl = 0;
396 /* Calculate and program a divisor */
397 if (rate > 0x100000 * HZ) {
399 ctrl |= TIMER_CTRL_DIV256;
400 } else if (rate > 0x10000 * HZ) {
402 ctrl |= TIMER_CTRL_DIV16;
404 timer_reload = rate / HZ;
405 writel(ctrl, clkevt_base + TIMER_CTRL);
407 setup_irq(irq, &integrator_timer_irq);
408 clockevents_config_and_register(&integrator_clockevent,
414 void __init ap_init_early(void)
420 static void __init ap_of_timer_init(void)
422 struct device_node *node;
430 clk = clk_get_sys("ap_timer", NULL);
432 clk_prepare_enable(clk);
433 rate = clk_get_rate(clk);
435 err = of_property_read_string(of_aliases,
436 "arm,timer-primary", &path);
439 node = of_find_node_by_path(path);
440 base = of_iomap(node, 0);
443 writel(0, base + TIMER_CTRL);
444 integrator_clocksource_init(rate, base);
446 err = of_property_read_string(of_aliases,
447 "arm,timer-secondary", &path);
450 node = of_find_node_by_path(path);
451 base = of_iomap(node, 0);
454 irq = irq_of_parse_and_map(node, 0);
455 writel(0, base + TIMER_CTRL);
456 integrator_clockevent_init(rate, base, irq);
459 static const struct of_device_id fpga_irq_of_match[] __initconst = {
460 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
464 static void __init ap_init_irq_of(void)
466 /* disable core module IRQs */
467 writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
468 of_irq_init(fpga_irq_of_match);
469 integrator_clk_init(false);
472 /* For the Device Tree, add in the UART callbacks as AUXDATA */
473 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
474 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
476 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
477 "uart0", &ap_uart_data),
478 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
479 "uart1", &ap_uart_data),
480 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
482 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
484 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
485 "physmap-flash", &ap_flash_data),
490 * This is a placeholder that will get deleted when we move the PCI
491 * device over to the device tree.
493 static struct platform_device pci_v3_device_of = {
498 static void __init ap_init_of(void)
500 unsigned long sc_dec;
501 struct device_node *root;
502 struct device_node *syscon;
503 struct device *parent;
504 struct soc_device *soc_dev;
505 struct soc_device_attribute *soc_dev_attr;
510 /* Here we create an SoC device for the root node */
511 root = of_find_node_by_path("/");
514 syscon = of_find_node_by_path("/syscon");
518 ap_syscon_base = of_iomap(syscon, 0);
522 ap_sc_id = readl(ap_syscon_base);
524 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
528 err = of_property_read_string(root, "compatible",
529 &soc_dev_attr->soc_id);
532 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
535 soc_dev_attr->family = "Integrator";
536 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
537 'A' + (ap_sc_id & 0x0f));
539 soc_dev = soc_device_register(soc_dev_attr);
540 if (IS_ERR(soc_dev)) {
541 kfree(soc_dev_attr->revision);
546 parent = soc_device_to_device(soc_dev);
547 integrator_init_sysfs(parent, ap_sc_id);
549 of_platform_populate(root, of_default_bus_match_table,
550 ap_auxdata_lookup, parent);
552 platform_device_register(&pci_v3_device_of);
554 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
555 for (i = 0; i < 4; i++) {
556 struct lm_device *lmdev;
558 if ((sc_dec & (16 << i)) == 0)
561 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
565 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
566 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
567 lmdev->resource.flags = IORESOURCE_MEM;
568 lmdev->irq = IRQ_AP_EXPINT0 + i;
571 lm_device_register(lmdev);
575 static const char * ap_dt_board_compat[] = {
580 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
581 .reserve = integrator_reserve,
583 .init_early = ap_init_early,
584 .init_irq = ap_init_irq_of,
585 .handle_irq = fpga_handle_irq,
586 .init_time = ap_of_timer_init,
587 .init_machine = ap_init_of,
588 .restart = integrator_restart,
589 .dt_compat = ap_dt_board_compat,
597 * For the ATAG boot some static mappings are needed. This will
598 * go away with the ATAG support down the road.
601 static struct map_desc ap_io_desc_atag[] __initdata = {
603 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
604 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
610 static void __init ap_map_io_atag(void)
612 iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
617 * This is where non-devicetree initialization code is collected and stashed
618 * for eventual deletion.
621 static struct platform_device pci_v3_device = {
626 static struct resource cfi_flash_resource = {
627 .start = INTEGRATOR_FLASH_BASE,
628 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
629 .flags = IORESOURCE_MEM,
632 static struct platform_device cfi_flash_device = {
633 .name = "physmap-flash",
636 .platform_data = &ap_flash_data,
639 .resource = &cfi_flash_resource,
642 static void __init ap_timer_init(void)
647 clk = clk_get_sys("ap_timer", NULL);
649 clk_prepare_enable(clk);
650 rate = clk_get_rate(clk);
652 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
653 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
654 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
656 integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
657 integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
661 #define INTEGRATOR_SC_VALID_INT 0x003fffff
663 static void __init ap_init_irq(void)
665 /* Disable all interrupts initially. */
666 /* Do the core module ones */
667 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
669 /* do the header card stuff next */
670 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
671 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
673 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
674 -1, INTEGRATOR_SC_VALID_INT, NULL);
675 integrator_clk_init(false);
678 static void __init ap_init(void)
680 unsigned long sc_dec;
683 platform_device_register(&pci_v3_device);
684 platform_device_register(&cfi_flash_device);
686 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
687 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
688 for (i = 0; i < 4; i++) {
689 struct lm_device *lmdev;
691 if ((sc_dec & (16 << i)) == 0)
694 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
698 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
699 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
700 lmdev->resource.flags = IORESOURCE_MEM;
701 lmdev->irq = IRQ_AP_EXPINT0 + i;
704 lm_device_register(lmdev);
707 integrator_init(false);
710 MACHINE_START(INTEGRATOR, "ARM-Integrator")
711 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
712 .atag_offset = 0x100,
713 .reserve = integrator_reserve,
714 .map_io = ap_map_io_atag,
715 .init_early = ap_init_early,
716 .init_irq = ap_init_irq,
717 .handle_irq = fpga_handle_irq,
718 .init_time = ap_timer_init,
719 .init_machine = ap_init,
720 .restart = integrator_restart,