1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/boot_mode.h>
12 #include <asm/mach-imx/hab.h>
14 #define PMC0_BASE_ADDR 0x410a1000
15 #define PMC0_CTRL 0x28
16 #define PMC0_CTRL_LDOEN BIT(31)
17 #define PMC0_CTRL_LDOOKDIS BIT(30)
18 #define PMC0_CTRL_PMC1ON BIT(24)
19 #define PMC1_BASE_ADDR 0x40400000
21 #define PMC1_STOP 0x10
22 #define PMC1_VLPS 0x14
23 #define PMC1_LDOVL_SHIFT 16
24 #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
25 #define PMC1_LDOVL_900 0x1e
26 #define PMC1_LDOVL_950 0x23
27 #define PMC1_STATUS 0x20
28 #define PMC1_STATUS_LDOVLF BIT(8)
30 static char *get_reset_cause(char *);
32 #if defined(CONFIG_IMX_HAB)
33 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
39 #define ROM_VERSION_ADDR 0x80
42 /* Check the ROM version for cpu revision */
43 u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
45 return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
48 #ifdef CONFIG_REVISION_TAG
49 u32 __weak get_board_rev(void)
55 enum bt_mode get_boot_mode(void)
59 bt0_cfg = readl(CMC0_RBASE + 0x40);
60 bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
62 if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
63 /* No low power boot */
64 if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
70 return LOW_POWER_BOOT;
73 int arch_cpu_init(void)
78 #ifdef CONFIG_BOARD_POSTCLK_INIT
79 int board_postclk_init(void)
85 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
86 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
87 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
88 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
90 static void disable_wdog(u32 wdog_base)
92 writel(UNLOCK_WORD0, (wdog_base + 0x04));
93 writel(UNLOCK_WORD1, (wdog_base + 0x04));
94 writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
95 writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
96 writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
98 writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
99 writel(REFRESH_WORD1, (wdog_base + 0x04));
105 * ROM will configure WDOG1, disable it or enable it
106 * depending on FUSE. The update bit is set for reconfigurable.
107 * We have to use unlock sequence to reconfigure it.
108 * WDOG2 is not touched by ROM, so it will have default value
109 * which is enabled. We can directly configure it.
110 * To simplify the codes, we still use same reconfigure
111 * process as WDOG1. Because the update bit is not set for
112 * WDOG2, the unlock sequence won't take effect really.
113 * It actually directly configure the wdog.
114 * In this function, we will disable both WDOG1 and WDOG2,
115 * and set update bit for both. So that kernel can reconfigure them.
117 disable_wdog(WDG1_RBASE);
118 disable_wdog(WDG2_RBASE);
121 #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
122 #if defined(CONFIG_LDO_ENABLED_MODE)
123 static void init_ldo_mode(void)
128 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
130 /* Set LDOVL to 0.95V in PMC1_RUN */
131 reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
132 reg &= ~PMC1_LDOVL_MASK;
133 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
134 writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
136 /* Wait for LDOVLF to be cleared */
137 reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
138 while (reg & PMC1_STATUS_LDOVLF)
141 /* Set LDOVL to 0.95V in PMC1_STOP */
142 reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
143 reg &= ~PMC1_LDOVL_MASK;
144 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
145 writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
147 /* Set LDOVL to 0.90V in PMC1_VLPS */
148 reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
149 reg &= ~PMC1_LDOVL_MASK;
150 reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
151 writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
154 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
156 /* Set the PMC1ON bit */
157 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
166 /* clock configuration. */
169 if (soc_rev() < CHIP_REV_2_0) {
170 /* enable dumb pmic */
171 writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
174 #if defined(CONFIG_LDO_ENABLED_MODE)
181 #ifndef CONFIG_ULP_WATCHDOG
182 void reset_cpu(ulong addr)
184 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
190 #if defined(CONFIG_DISPLAY_CPUINFO)
191 const char *get_imx_type(u32 imxtype)
196 #define PMC0_BASE_ADDR 0x410a1000
197 #define PMC0_CTRL 0x28
198 #define PMC0_CTRL_LDOEN BIT(31)
200 static bool ldo_mode_is_enabled(void)
204 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
205 if (reg & PMC0_CTRL_LDOEN)
211 int print_cpuinfo(void)
216 cpurev = get_cpu_rev();
218 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
219 get_imx_type((cpurev & 0xFF000) >> 12),
220 (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
221 mxc_get_clock(MXC_ARM_CLK) / 1000000);
223 printf("Reset cause: %s\n", get_reset_cause(cause));
225 printf("Boot mode: ");
226 switch (get_boot_mode()) {
228 printf("Low power boot\n");
231 printf("Dual boot\n");
235 printf("Single boot\n");
239 if (ldo_mode_is_enabled())
240 printf("PMC1: LDO enabled mode\n");
242 printf("PMC1: LDO bypass mode\n");
248 #define CMC_SRS_TAMPER (1 << 31)
249 #define CMC_SRS_SECURITY (1 << 30)
250 #define CMC_SRS_TZWDG (1 << 29)
251 #define CMC_SRS_JTAG_RST (1 << 28)
252 #define CMC_SRS_CORE1 (1 << 16)
253 #define CMC_SRS_LOCKUP (1 << 15)
254 #define CMC_SRS_SW (1 << 14)
255 #define CMC_SRS_WDG (1 << 13)
256 #define CMC_SRS_PIN_RESET (1 << 8)
257 #define CMC_SRS_WARM (1 << 4)
258 #define CMC_SRS_HVD (1 << 3)
259 #define CMC_SRS_LVD (1 << 2)
260 #define CMC_SRS_POR (1 << 1)
261 #define CMC_SRS_WUP (1 << 0)
263 static u32 reset_cause = -1;
265 static char *get_reset_cause(char *ret)
267 u32 cause1, cause = 0, srs = 0;
268 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
269 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
274 srs = readl(reg_srs);
275 cause1 = readl(reg_ssrs);
276 writel(cause1, reg_ssrs);
278 reset_cause = cause1;
280 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
284 sprintf(ret, "%s", "POR");
287 sprintf(ret, "%s", "WUP");
290 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
294 sprintf(ret, "%s", "WARM-WDG");
297 sprintf(ret, "%s", "WARM-SW");
299 case CMC_SRS_JTAG_RST:
300 sprintf(ret, "%s", "WARM-JTAG");
303 sprintf(ret, "%s", "WARM-UNKN");
308 sprintf(ret, "%s-%X", "UNKN", cause1);
312 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
316 #ifdef CONFIG_ENV_IS_IN_MMC
317 __weak int board_mmc_get_env_dev(int devno)
319 return CONFIG_SYS_MMC_ENV_DEV;
322 int mmc_get_env_dev(void)
327 /* If not boot from sd/mmc, use default value */
328 if (get_boot_mode() == LOW_POWER_BOOT)
329 return CONFIG_SYS_MMC_ENV_DEV;
331 bt1_cfg = readl(CMC1_RBASE + 0x40);
332 devno = (bt1_cfg >> 9) & 0x7;
334 return board_mmc_get_env_dev(devno);
338 enum boot_device get_boot_device(void)
340 struct bootrom_sw_info **p =
341 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
343 enum boot_device boot_dev = SD1_BOOT;
344 u8 boot_type = (*p)->boot_dev_type;
345 u8 boot_instance = (*p)->boot_dev_instance;
349 boot_dev = boot_instance + SD1_BOOT;
352 boot_dev = boot_instance + MMC1_BOOT;