1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
7 #include <clock_legacy.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
15 DECLARE_GLOBAL_DATA_PTR;
19 #ifdef CONFIG_FSL_ESDHC_IMX
20 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
21 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
22 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
23 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
29 static u32 get_fast_plat_clk(void)
31 return scg_clk_get_rate(SCG_NIC0_CLK);
34 static u32 get_slow_plat_clk(void)
36 return scg_clk_get_rate(SCG_NIC1_CLK);
39 static u32 get_ipg_clk(void)
41 return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
44 u32 get_lpuart_clk(void)
48 const u32 lpuart_array[] = {
59 const enum pcc_clk lpuart_pcc_clks[] = {
66 for (index = 0; index < 8; index++) {
67 if (lpuart_array[index] == LPUART_BASE)
71 if (index < 4 || index > 7)
74 return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
77 #ifdef CONFIG_SYS_I2C_IMX_LPI2C
78 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
80 /* Set parent to FIRC DIV2 clock */
81 const enum pcc_clk lpi2c_pcc_clks[] = {
88 if (i2c_num < 4 || i2c_num > 7)
92 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
93 pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
94 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
96 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
101 u32 imx_get_i2cclk(unsigned i2c_num)
103 const enum pcc_clk lpi2c_pcc_clks[] = {
110 if (i2c_num < 4 || i2c_num > 7)
113 return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
117 unsigned int mxc_get_clock(enum mxc_clock clk)
121 return scg_clk_get_rate(SCG_CORE_CLK);
123 return get_fast_plat_clk();
125 return get_slow_plat_clk();
127 return get_ipg_clk();
129 return pcc_clock_get_rate(PER_CLK_LPI2C4);
131 return get_lpuart_clk();
133 return pcc_clock_get_rate(PER_CLK_USDHC0);
135 return pcc_clock_get_rate(PER_CLK_USDHC1);
137 return scg_clk_get_rate(SCG_DDR_CLK);
139 printf("Unsupported mxc_clock %d\n", clk);
146 void init_clk_usdhc(u32 index)
150 /*Disable the clock before configure it */
151 pcc_clock_enable(PER_CLK_USDHC0, false);
153 /* 158MHz / 1 = 158MHz */
154 pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
155 pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
156 pcc_clock_enable(PER_CLK_USDHC0, true);
159 /*Disable the clock before configure it */
160 pcc_clock_enable(PER_CLK_USDHC1, false);
162 /* 158MHz / 1 = 158MHz */
163 pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
164 pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
165 pcc_clock_enable(PER_CLK_USDHC1, true);
168 printf("Invalid index for USDHC %d\n", index);
173 #ifdef CONFIG_MXC_OCOTP
175 #define OCOTP_CTRL_PCC1_SLOT (38)
176 #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
178 void enable_ocotp_clk(unsigned char enable)
183 * Seems the OCOTP CLOCKs have been enabled at default,
184 * check its inuse flag
187 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
188 if (!(val & PCC_INUSE_MASK))
189 writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
191 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
192 if (!(val & PCC_INUSE_MASK))
194 (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
198 void enable_usboh3_clk(unsigned char enable)
201 pcc_clock_enable(PER_CLK_USB0, false);
202 pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
203 pcc_clock_enable(PER_CLK_USB0, true);
205 #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
206 if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
207 pcc_clock_enable(PER_CLK_USB1, false);
208 pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
209 pcc_clock_enable(PER_CLK_USB1, true);
213 pcc_clock_enable(PER_CLK_USB_PHY, true);
214 pcc_clock_enable(PER_CLK_USB_PL301, true);
216 pcc_clock_enable(PER_CLK_USB0, false);
217 pcc_clock_enable(PER_CLK_USB1, false);
218 pcc_clock_enable(PER_CLK_USB_PHY, false);
219 pcc_clock_enable(PER_CLK_USB_PL301, false);
223 static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
225 const enum pcc_clk lpuart_pcc_clks[] = {
232 if (index < 4 || index > 7)
235 #ifndef CONFIG_CLK_DEBUG
236 pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
238 pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
239 pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
242 static void init_clk_lpuart(void)
246 const u32 lpuart_array[] = {
257 for (i = 0; i < 8; i++) {
258 if (lpuart_array[i] == LPUART_BASE) {
264 lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
267 static void init_clk_rgpio2p(void)
269 /*Enable RGPIO2P1 clock */
270 pcc_clock_enable(PER_CLK_RGPIO2P1, true);
273 * Hard code to enable RGPIO2P0 clock since it is not
274 * in clock frame for A7 domain
276 writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
279 /* Configure PLL/PFD freq */
280 void clock_init(void)
283 * ROM has enabled clocks:
284 * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
285 * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
286 * A7 side: SPLL PFD0 (scs selected, 413Mhz),
287 * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
288 * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
289 * IP BUS (NIC1_BUS) = 58.6Mhz
292 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
294 * 3. Init the clocks of peripherals used in u-boot bu
295 * without set rate interface.The clocks for these
296 * peripherals are enabled in this intialization.
297 * 4.Other peripherals with set clock rate interface
298 * does not be set in this function.
303 scg_a7_soscdiv_init();
305 scg_a7_init_core_clk();
307 /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
308 scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
309 scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
310 scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
316 enable_usboh3_clk(1);
319 #ifdef CONFIG_IMX_HAB
320 void hab_caam_clock_enable(unsigned char enable)
323 pcc_clock_enable(PER_CLK_CAAM, true);
325 pcc_clock_enable(PER_CLK_CAAM, false);
329 #ifndef CONFIG_SPL_BUILD
331 * Dump some core clockes.
333 int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
338 freq = decode_pll(PLL_A7_SPLL);
339 printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
341 freq = decode_pll(PLL_A7_APLL);
342 printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
344 freq = decode_pll(PLL_USB);
345 printf("PLL_USB %8d MHz\n", freq / 1000000);
349 printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
350 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
351 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
352 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
353 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
354 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
355 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
356 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
357 printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
359 addr = (u32) clock_init;
360 printf("[%s] addr = 0x%08X\r\n", __func__, addr);
367 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,