1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
13 DECLARE_GLOBAL_DATA_PTR;
17 #ifdef CONFIG_FSL_ESDHC_IMX
18 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
19 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
20 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
21 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
27 static u32 get_fast_plat_clk(void)
29 return scg_clk_get_rate(SCG_NIC0_CLK);
32 static u32 get_slow_plat_clk(void)
34 return scg_clk_get_rate(SCG_NIC1_CLK);
37 static u32 get_ipg_clk(void)
39 return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
42 u32 get_lpuart_clk(void)
46 const u32 lpuart_array[] = {
57 const enum pcc_clk lpuart_pcc_clks[] = {
64 for (index = 0; index < 8; index++) {
65 if (lpuart_array[index] == LPUART_BASE)
69 if (index < 4 || index > 7)
72 return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
75 #ifdef CONFIG_SYS_I2C_IMX_LPI2C
76 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
78 /* Set parent to FIRC DIV2 clock */
79 const enum pcc_clk lpi2c_pcc_clks[] = {
86 if (i2c_num < 4 || i2c_num > 7)
90 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
91 pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
92 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
94 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
99 u32 imx_get_i2cclk(unsigned i2c_num)
101 const enum pcc_clk lpi2c_pcc_clks[] = {
108 if (i2c_num < 4 || i2c_num > 7)
111 return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
115 unsigned int mxc_get_clock(enum mxc_clock clk)
119 return scg_clk_get_rate(SCG_CORE_CLK);
121 return get_fast_plat_clk();
123 return get_slow_plat_clk();
125 return get_ipg_clk();
127 return pcc_clock_get_rate(PER_CLK_LPI2C4);
129 return get_lpuart_clk();
131 return pcc_clock_get_rate(PER_CLK_USDHC0);
133 return pcc_clock_get_rate(PER_CLK_USDHC1);
135 return scg_clk_get_rate(SCG_DDR_CLK);
137 printf("Unsupported mxc_clock %d\n", clk);
144 void init_clk_usdhc(u32 index)
148 /*Disable the clock before configure it */
149 pcc_clock_enable(PER_CLK_USDHC0, false);
151 /* 158MHz / 1 = 158MHz */
152 pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
153 pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
154 pcc_clock_enable(PER_CLK_USDHC0, true);
157 /*Disable the clock before configure it */
158 pcc_clock_enable(PER_CLK_USDHC1, false);
160 /* 158MHz / 1 = 158MHz */
161 pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
162 pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
163 pcc_clock_enable(PER_CLK_USDHC1, true);
166 printf("Invalid index for USDHC %d\n", index);
171 #ifdef CONFIG_MXC_OCOTP
173 #define OCOTP_CTRL_PCC1_SLOT (38)
174 #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
176 void enable_ocotp_clk(unsigned char enable)
181 * Seems the OCOTP CLOCKs have been enabled at default,
182 * check its inuse flag
185 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
186 if (!(val & PCC_INUSE_MASK))
187 writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
189 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
190 if (!(val & PCC_INUSE_MASK))
192 (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
196 void enable_usboh3_clk(unsigned char enable)
199 pcc_clock_enable(PER_CLK_USB0, false);
200 pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
201 pcc_clock_enable(PER_CLK_USB0, true);
203 #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
204 if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
205 pcc_clock_enable(PER_CLK_USB1, false);
206 pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
207 pcc_clock_enable(PER_CLK_USB1, true);
211 pcc_clock_enable(PER_CLK_USB_PHY, true);
212 pcc_clock_enable(PER_CLK_USB_PL301, true);
214 pcc_clock_enable(PER_CLK_USB0, false);
215 pcc_clock_enable(PER_CLK_USB1, false);
216 pcc_clock_enable(PER_CLK_USB_PHY, false);
217 pcc_clock_enable(PER_CLK_USB_PL301, false);
221 static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
223 const enum pcc_clk lpuart_pcc_clks[] = {
230 if (index < 4 || index > 7)
233 #ifndef CONFIG_CLK_DEBUG
234 pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
236 pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
237 pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
240 static void init_clk_lpuart(void)
244 const u32 lpuart_array[] = {
255 for (i = 0; i < 8; i++) {
256 if (lpuart_array[i] == LPUART_BASE) {
262 lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
265 static void init_clk_rgpio2p(void)
267 /*Enable RGPIO2P1 clock */
268 pcc_clock_enable(PER_CLK_RGPIO2P1, true);
271 * Hard code to enable RGPIO2P0 clock since it is not
272 * in clock frame for A7 domain
274 writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
277 /* Configure PLL/PFD freq */
278 void clock_init(void)
281 * ROM has enabled clocks:
282 * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
283 * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
284 * A7 side: SPLL PFD0 (scs selected, 413Mhz),
285 * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
286 * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
287 * IP BUS (NIC1_BUS) = 58.6Mhz
290 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
292 * 3. Init the clocks of peripherals used in u-boot bu
293 * without set rate interface.The clocks for these
294 * peripherals are enabled in this intialization.
295 * 4.Other peripherals with set clock rate interface
296 * does not be set in this function.
301 scg_a7_soscdiv_init();
303 /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
304 scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
305 scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
306 scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
312 enable_usboh3_clk(1);
315 #ifdef CONFIG_SECURE_BOOT
316 void hab_caam_clock_enable(unsigned char enable)
319 pcc_clock_enable(PER_CLK_CAAM, true);
321 pcc_clock_enable(PER_CLK_CAAM, false);
325 #ifndef CONFIG_SPL_BUILD
327 * Dump some core clockes.
329 int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
333 freq = decode_pll(PLL_A7_SPLL);
334 printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
336 freq = decode_pll(PLL_A7_APLL);
337 printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
339 freq = decode_pll(PLL_USB);
340 printf("PLL_USB %8d MHz\n", freq / 1000000);
344 printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
345 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
346 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
347 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
348 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
349 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
350 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
351 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
352 printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
354 addr = (u32) clock_init;
355 printf("[%s] addr = 0x%08X\r\n", __func__, addr);
362 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,