1 // SPDX-License-Identifier: GPL-2.0+
3 * DDR controller configuration for the i.MX7 architecture
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
10 #include <linux/types.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/mx7-ddr.h>
16 #include <linux/delay.h>
19 * Routine: mx7_dram_cfg
20 * Description: DDR controller configuration
22 * @ddrc_regs_val: DDRC registers value
23 * @ddrc_mp_val: DDRC_MP registers value
24 * @ddr_phy_regs_val: DDR_PHY registers value
25 * @calib_param: calibration parameters
28 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
29 struct ddr_phy *ddr_phy_regs_val,
30 struct mx7_calibration *calib_param)
32 struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
33 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
34 struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
35 struct ddr_phy *const ddr_phy_regs =
36 (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
37 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
38 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
42 * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
43 * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
44 * aresetn_n = 0, presetn = 0. That means reset everything.
46 writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
50 * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
51 * If we assume this is 30 cycles at 100 MHz (about the rate of a
52 * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
56 /* De-assert DDR Controller 'preset' and DDR PHY reset */
57 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
59 /* DDR controller configuration */
60 writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
61 writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
62 writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
63 writel(ddrc_regs_val->init1, &ddrc_regs->init1);
64 writel(ddrc_regs_val->init0, &ddrc_regs->init0);
65 writel(ddrc_regs_val->init3, &ddrc_regs->init3);
66 writel(ddrc_regs_val->init4, &ddrc_regs->init4);
67 writel(ddrc_regs_val->init5, &ddrc_regs->init5);
68 writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
69 writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
70 writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
71 writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
72 writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
73 writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
74 writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
75 writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
76 writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
77 writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
78 writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
79 writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
80 writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
81 writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
82 writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
83 writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
84 writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
85 writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
86 writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
87 writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
88 writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
90 /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
91 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
93 /* PHY configuration */
94 writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
95 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
96 writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
97 writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
98 writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
99 writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
100 writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
101 writel(ddr_phy_regs_val->cmd_sdll_con0 |
102 DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
103 &ddr_phy_regs->cmd_sdll_con0);
104 writel(ddr_phy_regs_val->cmd_sdll_con0 &
105 ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
106 &ddr_phy_regs->cmd_sdll_con0);
107 writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
110 for (i = 0; i < calib_param->num_val; i++)
111 writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
113 /* Wake_up DDR PHY */
114 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
115 writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
116 IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
117 &iomuxc_gpr_regs->gpr[8]);
118 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
122 * Routine: imx_ddr_size
123 * Description: extract the current DRAM size from the DDRC registers
127 unsigned int imx_ddr_size(void)
129 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
130 u32 reg_val, field_val;
131 int bits = 0;/* Number of address bits */
133 /* Count data bus width bits */
134 reg_val = readl(&ddrc_regs->mstr);
135 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
136 bits += 2 - field_val;
137 /* Count rank address bits */
138 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
140 bits += field_val - 1;
141 /* Count column address bits */
142 bits += 2;/* Column address 0 and 1 are fixed mapped */
143 reg_val = readl(&ddrc_regs->addrmap2);
144 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
147 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
150 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
153 field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
156 reg_val = readl(&ddrc_regs->addrmap3);
157 field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
160 field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
163 field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
166 field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
169 reg_val = readl(&ddrc_regs->addrmap4);
170 field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
173 field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
176 /* Count row address bits */
177 reg_val = readl(&ddrc_regs->addrmap5);
178 field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
181 field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
184 field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
187 field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
190 reg_val = readl(&ddrc_regs->addrmap6);
191 field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
194 field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
197 field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
200 field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
203 /* Count bank bits */
204 reg_val = readl(&ddrc_regs->addrmap1);
205 field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
208 field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
211 field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
215 /* cap to max 2 GB */