1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 * Peng Fan <Peng.Fan@freescale.com>
10 #include <clock_legacy.h>
15 #include <linux/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
21 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
23 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_FSL_ESDHC_IMX
26 DECLARE_GLOBAL_DATA_PTR;
31 #ifdef CONFIG_FSL_ESDHC_IMX
32 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
33 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
34 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
37 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
45 return get_root_clk(AHB_CLK_ROOT);
48 static u32 get_ipg_clk(void)
51 * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
54 return get_ahb_clk() / 2;
57 u32 imx_get_uartclk(void)
59 return get_root_clk(UART_CLK_ROOT);
62 u32 imx_get_fecclk(void)
64 return get_root_clk(ENET_AXI_CLK_ROOT);
67 #ifdef CONFIG_MXC_OCOTP
68 void enable_ocotp_clk(unsigned char enable)
70 clock_enable(CCGR_OCOTP, enable);
73 void enable_thermal_clk(void)
79 void enable_usboh3_clk(unsigned char enable)
84 /* disable the clock gate first */
85 clock_enable(CCGR_USB_HSIC, 0);
88 target = CLK_ROOT_ON |
89 USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
90 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
91 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
92 clock_set_target_val(USB_HSIC_CLK_ROOT, target);
94 /* enable the clock gate */
95 clock_enable(CCGR_USB_CTRL, 1);
96 clock_enable(CCGR_USB_HSIC, 1);
97 clock_enable(CCGR_USB_PHY1, 1);
98 clock_enable(CCGR_USB_PHY2, 1);
100 clock_enable(CCGR_USB_CTRL, 0);
101 clock_enable(CCGR_USB_HSIC, 0);
102 clock_enable(CCGR_USB_PHY1, 0);
103 clock_enable(CCGR_USB_PHY2, 0);
107 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
113 * Alought there are four choices for the bypass src,
114 * we choose OSC_24M which is the default set in ROM.
118 reg = readl(&ccm_anatop->pll_arm);
120 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
123 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
126 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
127 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
129 return (infreq * div_sel) / 2;
132 reg = readl(&ccm_anatop->pll_480);
134 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
137 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
140 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
141 CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
147 reg = readl(&ccm_anatop->pll_enet);
149 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
152 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
158 reg = readl(&ccm_anatop->pll_ddr);
160 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
163 num = ccm_anatop->pll_ddr_num;
164 denom = ccm_anatop->pll_ddr_denom;
166 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
169 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
170 CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
172 return infreq * (div_sel + num / denom);
178 printf("Unsupported pll clocks %d\n", pll);
185 static u32 mxc_get_pll_sys_derive(int derive)
191 reg = readl(&ccm_anatop->pll_480);
192 freq = decode_pll(PLL_SYS, MXC_HCLK);
195 case PLL_SYS_MAIN_480M_CLK:
196 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
200 case PLL_SYS_MAIN_240M_CLK:
201 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
205 case PLL_SYS_MAIN_120M_CLK:
206 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
210 case PLL_SYS_PFD0_392M_CLK:
211 reg = readl(&ccm_anatop->pfd_480a);
212 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
214 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
215 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
217 case PLL_SYS_PFD0_196M_CLK:
218 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
220 reg = readl(&ccm_anatop->pfd_480a);
221 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
222 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
225 case PLL_SYS_PFD1_332M_CLK:
226 reg = readl(&ccm_anatop->pfd_480a);
227 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
229 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
230 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
232 case PLL_SYS_PFD1_166M_CLK:
233 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
235 reg = readl(&ccm_anatop->pfd_480a);
236 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
237 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
240 case PLL_SYS_PFD2_270M_CLK:
241 reg = readl(&ccm_anatop->pfd_480a);
242 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
244 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
245 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
247 case PLL_SYS_PFD2_135M_CLK:
248 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
250 reg = readl(&ccm_anatop->pfd_480a);
251 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
252 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
255 case PLL_SYS_PFD3_CLK:
256 reg = readl(&ccm_anatop->pfd_480a);
257 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
259 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
260 CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
262 case PLL_SYS_PFD4_CLK:
263 reg = readl(&ccm_anatop->pfd_480b);
264 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
266 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
267 CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
269 case PLL_SYS_PFD5_CLK:
270 reg = readl(&ccm_anatop->pfd_480b);
271 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
273 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
274 CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
276 case PLL_SYS_PFD6_CLK:
277 reg = readl(&ccm_anatop->pfd_480b);
278 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
280 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
281 CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
283 case PLL_SYS_PFD7_CLK:
284 reg = readl(&ccm_anatop->pfd_480b);
285 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
287 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
288 CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
291 printf("Error derived pll_sys clock %d\n", derive);
295 return ((freq / frac) * 18) / div;
298 static u32 mxc_get_pll_enet_derive(int derive)
302 freq = decode_pll(PLL_ENET, MXC_HCLK);
303 reg = readl(&ccm_anatop->pll_enet);
306 case PLL_ENET_MAIN_500M_CLK:
307 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
310 case PLL_ENET_MAIN_250M_CLK:
311 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
314 case PLL_ENET_MAIN_125M_CLK:
315 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
318 case PLL_ENET_MAIN_100M_CLK:
319 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
322 case PLL_ENET_MAIN_50M_CLK:
323 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
326 case PLL_ENET_MAIN_40M_CLK:
327 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
330 case PLL_ENET_MAIN_25M_CLK:
331 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
335 printf("Error derived pll_enet clock %d\n", derive);
342 static u32 mxc_get_pll_ddr_derive(int derive)
346 freq = decode_pll(PLL_DDR, MXC_HCLK);
347 reg = readl(&ccm_anatop->pll_ddr);
350 case PLL_DRAM_MAIN_1066M_CLK:
352 case PLL_DRAM_MAIN_533M_CLK:
353 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
357 printf("Error derived pll_ddr clock %d\n", derive);
364 static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
368 return mxc_get_pll_sys_derive(derive);
370 return mxc_get_pll_enet_derive(derive);
372 return mxc_get_pll_ddr_derive(derive);
374 printf("Error pll.\n");
379 static u32 get_root_src_clk(enum clk_root_src root_src)
384 case PLL_ARM_MAIN_800M_CLK:
385 return decode_pll(PLL_CORE, MXC_HCLK);
387 case PLL_SYS_MAIN_480M_CLK:
388 case PLL_SYS_MAIN_240M_CLK:
389 case PLL_SYS_MAIN_120M_CLK:
390 case PLL_SYS_PFD0_392M_CLK:
391 case PLL_SYS_PFD0_196M_CLK:
392 case PLL_SYS_PFD1_332M_CLK:
393 case PLL_SYS_PFD1_166M_CLK:
394 case PLL_SYS_PFD2_270M_CLK:
395 case PLL_SYS_PFD2_135M_CLK:
396 case PLL_SYS_PFD3_CLK:
397 case PLL_SYS_PFD4_CLK:
398 case PLL_SYS_PFD5_CLK:
399 case PLL_SYS_PFD6_CLK:
400 case PLL_SYS_PFD7_CLK:
401 return mxc_get_pll_derive(PLL_SYS, root_src);
403 case PLL_ENET_MAIN_500M_CLK:
404 case PLL_ENET_MAIN_250M_CLK:
405 case PLL_ENET_MAIN_125M_CLK:
406 case PLL_ENET_MAIN_100M_CLK:
407 case PLL_ENET_MAIN_50M_CLK:
408 case PLL_ENET_MAIN_40M_CLK:
409 case PLL_ENET_MAIN_25M_CLK:
410 return mxc_get_pll_derive(PLL_ENET, root_src);
412 case PLL_DRAM_MAIN_1066M_CLK:
413 case PLL_DRAM_MAIN_533M_CLK:
414 return mxc_get_pll_derive(PLL_DDR, root_src);
416 case PLL_AUDIO_MAIN_CLK:
417 return decode_pll(PLL_AUDIO, MXC_HCLK);
418 case PLL_VIDEO_MAIN_CLK:
419 return decode_pll(PLL_VIDEO, MXC_HCLK);
421 case PLL_USB_MAIN_480M_CLK:
422 return decode_pll(PLL_USB, MXC_HCLK);
433 printf("No EXT CLK supported??\n");
440 u32 get_root_clk(enum clk_root_index clock_id)
442 enum clk_root_src root_src;
443 u32 post_podf, pre_podf, auto_podf, root_src_clk;
446 if (clock_root_enabled(clock_id) <= 0)
449 if (clock_get_prediv(clock_id, &pre_podf) < 0)
452 if (clock_get_postdiv(clock_id, &post_podf) < 0)
455 if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
461 if (clock_get_src(clock_id, &root_src) < 0)
464 root_src_clk = get_root_src_clk(root_src);
467 * bypass clk is ignored.
470 return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
474 static u32 get_ddrc_clk(void)
477 enum root_post_div post_div;
479 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
480 if (reg & CLK_ROOT_MUX_MASK)
481 /* DRAM_ALT_CLK_ROOT */
482 freq = get_root_clk(DRAM_ALT_CLK_ROOT);
484 /* PLL_DRAM_MAIN_1066M_CLK */
485 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
487 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
489 return freq / (post_div + 1) / 2;
492 unsigned int mxc_get_clock(enum mxc_clock clk)
496 return get_root_clk(ARM_A7_CLK_ROOT);
498 return get_root_clk(MAIN_AXI_CLK_ROOT);
500 return get_root_clk(AHB_CLK_ROOT);
502 return get_ipg_clk();
504 return get_root_clk(I2C1_CLK_ROOT);
506 return get_root_clk(UART1_CLK_ROOT);
508 return get_root_clk(ECSPI1_CLK_ROOT);
510 return get_ddrc_clk();
512 return get_root_clk(USDHC1_CLK_ROOT);
514 return get_root_clk(USDHC2_CLK_ROOT);
516 return get_root_clk(USDHC3_CLK_ROOT);
518 printf("Unsupported mxc_clock %d\n", clk);
525 #ifdef CONFIG_SYS_I2C_MXC
526 /* i2c_num can be 0 - 3 */
527 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
535 clock_enable(CCGR_I2C1 + i2c_num, 0);
537 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
539 target = CLK_ROOT_ON |
540 I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
541 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
542 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
543 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
545 clock_enable(CCGR_I2C1 + i2c_num, 1);
547 clock_enable(CCGR_I2C1 + i2c_num, 0);
554 static void init_clk_esdhc(void)
558 /* disable the clock gate first */
559 clock_enable(CCGR_USDHC1, 0);
560 clock_enable(CCGR_USDHC2, 0);
561 clock_enable(CCGR_USDHC3, 0);
564 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
565 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
566 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
567 clock_set_target_val(USDHC1_CLK_ROOT, target);
569 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
570 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
571 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
572 clock_set_target_val(USDHC2_CLK_ROOT, target);
574 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
575 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
576 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
577 clock_set_target_val(USDHC3_CLK_ROOT, target);
579 /* enable the clock gate */
580 clock_enable(CCGR_USDHC1, 1);
581 clock_enable(CCGR_USDHC2, 1);
582 clock_enable(CCGR_USDHC3, 1);
585 static void init_clk_uart(void)
589 /* disable the clock gate first */
590 clock_enable(CCGR_UART1, 0);
591 clock_enable(CCGR_UART2, 0);
592 clock_enable(CCGR_UART3, 0);
593 clock_enable(CCGR_UART4, 0);
594 clock_enable(CCGR_UART5, 0);
595 clock_enable(CCGR_UART6, 0);
596 clock_enable(CCGR_UART7, 0);
599 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
600 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
601 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
602 clock_set_target_val(UART1_CLK_ROOT, target);
604 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
605 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
606 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
607 clock_set_target_val(UART2_CLK_ROOT, target);
609 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
610 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
611 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
612 clock_set_target_val(UART3_CLK_ROOT, target);
614 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
615 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
616 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
617 clock_set_target_val(UART4_CLK_ROOT, target);
619 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
620 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
621 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
622 clock_set_target_val(UART5_CLK_ROOT, target);
624 target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
625 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
626 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
627 clock_set_target_val(UART6_CLK_ROOT, target);
629 target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
630 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
631 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
632 clock_set_target_val(UART7_CLK_ROOT, target);
634 /* enable the clock gate */
635 clock_enable(CCGR_UART1, 1);
636 clock_enable(CCGR_UART2, 1);
637 clock_enable(CCGR_UART3, 1);
638 clock_enable(CCGR_UART4, 1);
639 clock_enable(CCGR_UART5, 1);
640 clock_enable(CCGR_UART6, 1);
641 clock_enable(CCGR_UART7, 1);
644 static void init_clk_weim(void)
648 /* disable the clock gate first */
649 clock_enable(CCGR_WEIM, 0);
652 target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
653 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
654 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
655 clock_set_target_val(EIM_CLK_ROOT, target);
657 /* enable the clock gate */
658 clock_enable(CCGR_WEIM, 1);
661 static void init_clk_ecspi(void)
665 /* disable the clock gate first */
666 clock_enable(CCGR_ECSPI1, 0);
667 clock_enable(CCGR_ECSPI2, 0);
668 clock_enable(CCGR_ECSPI3, 0);
669 clock_enable(CCGR_ECSPI4, 0);
672 target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
673 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
674 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
675 clock_set_target_val(ECSPI1_CLK_ROOT, target);
677 target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
678 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
679 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
680 clock_set_target_val(ECSPI2_CLK_ROOT, target);
682 target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
683 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
684 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
685 clock_set_target_val(ECSPI3_CLK_ROOT, target);
687 target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
688 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
689 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
690 clock_set_target_val(ECSPI4_CLK_ROOT, target);
692 /* enable the clock gate */
693 clock_enable(CCGR_ECSPI1, 1);
694 clock_enable(CCGR_ECSPI2, 1);
695 clock_enable(CCGR_ECSPI3, 1);
696 clock_enable(CCGR_ECSPI4, 1);
699 static void init_clk_wdog(void)
703 /* disable the clock gate first */
704 clock_enable(CCGR_WDOG1, 0);
705 clock_enable(CCGR_WDOG2, 0);
706 clock_enable(CCGR_WDOG3, 0);
707 clock_enable(CCGR_WDOG4, 0);
710 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
711 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
712 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
713 clock_set_target_val(WDOG_CLK_ROOT, target);
715 /* enable the clock gate */
716 clock_enable(CCGR_WDOG1, 1);
717 clock_enable(CCGR_WDOG2, 1);
718 clock_enable(CCGR_WDOG3, 1);
719 clock_enable(CCGR_WDOG4, 1);
722 #ifdef CONFIG_MXC_EPDC
723 static void init_clk_epdc(void)
727 /* disable the clock gate first */
728 clock_enable(CCGR_EPDC, 0);
731 target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
732 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
733 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
734 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
736 /* enable the clock gate */
737 clock_enable(CCGR_EPDC, 1);
741 static int enable_pll_enet(void)
744 s32 timeout = 100000;
746 reg = readl(&ccm_anatop->pll_enet);
747 /* If pll_enet powered up, no need to set it again */
748 if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
749 reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
750 writel(reg, &ccm_anatop->pll_enet);
753 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
758 /* If timeout, we set pwdn for pll_enet. */
759 reg |= ANADIG_PLL_ENET_PWDN_MASK;
765 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
767 writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
768 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
769 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
770 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
771 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
772 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
773 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
774 &ccm_anatop->pll_enet_set);
778 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
784 debug("pll5 div = %d, num = %d, denom = %d\n",
785 pll_div, pll_num, pll_denom);
787 /* Power up PLL5 video and disable its output */
788 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
789 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
790 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
791 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
792 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
793 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
794 &ccm_anatop->pll_video_clr);
796 /* Set div, num and denom */
799 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
800 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
801 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
802 &ccm_anatop->pll_video_set);
805 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
806 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
807 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
808 &ccm_anatop->pll_video_set);
811 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
812 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
813 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
814 &ccm_anatop->pll_video_set);
817 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
818 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
819 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
820 &ccm_anatop->pll_video_set);
824 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
825 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
826 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
827 &ccm_anatop->pll_video_set);
831 writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
832 &ccm_anatop->pll_video_num);
834 writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
835 &ccm_anatop->pll_video_denom);
838 start = get_timer(0); /* Get current timestamp */
841 reg = readl(&ccm_anatop->pll_video);
842 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
844 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
845 &ccm_anatop->pll_video_set);
848 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
850 printf("Lock PLL5 timeout\n");
855 int set_clk_qspi(void)
859 /* disable the clock gate first */
860 clock_enable(CCGR_QSPI, 0);
863 target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
864 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
865 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
866 clock_set_target_val(QSPI_CLK_ROOT, target);
868 /* enable the clock gate */
869 clock_enable(CCGR_QSPI, 1);
874 int set_clk_nand(void)
878 /* disable the clock gate first */
879 clock_enable(CCGR_RAWNAND, 0);
883 target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
884 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
885 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
886 clock_set_target_val(NAND_CLK_ROOT, target);
888 /* enable the clock gate */
889 clock_enable(CCGR_RAWNAND, 1);
894 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
896 u32 hck = MXC_HCLK/1000;
900 u32 i, j, pred = 1, postd = 1;
901 u32 pll_div, pll_num, pll_denom, post_div = 0;
904 debug("mxs_set_lcdclk, freq = %d\n", freq);
906 clock_enable(CCGR_LCDIF, 0);
908 temp = (freq * 8 * 8);
910 for (i = 1; i <= 4; i++) {
911 if ((temp * (1 << i)) > min) {
913 freq = (freq * (1 << i));
919 printf("Fail to set rate to %dkhz", freq);
924 for (i = 1; i <= 8; i++) {
925 for (j = 1; j <= 8; j++) {
927 if (temp > max || temp < min)
930 if (best == 0 || temp < best) {
939 printf("Fail to set rate to %dkhz", freq);
943 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
945 pll_div = best / hck;
947 pll_num = (best - hck * pll_div) * pll_denom / hck;
949 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
952 target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
953 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
954 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
956 clock_enable(CCGR_LCDIF, 1);
959 #ifdef CONFIG_FEC_MXC
960 int set_clk_enet(enum enet_freq type)
964 u32 enet1_ref, enet2_ref;
966 /* disable the clock first */
967 clock_enable(CCGR_ENET1, 0);
968 clock_enable(CCGR_ENET2, 0);
972 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
973 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
976 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
977 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
980 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
981 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
987 ret = enable_pll_enet();
991 /* set enet axi clock 196M: 392/2 */
992 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
993 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
994 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
995 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
997 target = CLK_ROOT_ON | enet1_ref |
998 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
999 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1000 clock_set_target_val(ENET1_REF_CLK_ROOT, target);
1002 target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1003 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1004 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1005 clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
1007 target = CLK_ROOT_ON | enet2_ref |
1008 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1009 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1010 clock_set_target_val(ENET2_REF_CLK_ROOT, target);
1012 target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1013 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1014 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1015 clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
1017 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
1018 target = CLK_ROOT_ON |
1019 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
1020 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1021 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1022 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
1025 clock_enable(CCGR_ENET1, 1);
1026 clock_enable(CCGR_ENET2, 1);
1032 /* Configure PLL/PFD freq */
1033 void clock_init(void)
1035 /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
1036 * In u-boot, we have to:
1037 * 1. Configure PFD3- PFD7 for freq we needed in u-boot
1038 * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
1039 * interface. The clocks for these peripherals are enabled after this intialization.
1040 * 3. Other peripherals with set clock rate interface does not be set in this function.
1045 * Configure PFD4 to 392M
1046 * 480M * 18 / 0x16 = 392M
1048 reg = readl(&ccm_anatop->pfd_480b);
1050 reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
1051 CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
1052 reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
1054 writel(reg, &ccm_anatop->pfd_480b);
1061 #ifdef CONFIG_MXC_EPDC
1065 enable_usboh3_clk(1);
1067 clock_enable(CCGR_SNVS, 1);
1069 #ifdef CONFIG_NAND_MXS
1070 clock_enable(CCGR_RAWNAND, 1);
1073 if (IS_ENABLED(CONFIG_IMX_RDC)) {
1074 clock_enable(CCGR_RDC, 1);
1075 clock_enable(CCGR_SEMA1, 1);
1076 clock_enable(CCGR_SEMA2, 1);
1080 #ifdef CONFIG_IMX_HAB
1081 void hab_caam_clock_enable(unsigned char enable)
1084 clock_enable(CCGR_CAAM, 1);
1086 clock_enable(CCGR_CAAM, 0);
1090 #ifdef CONFIG_MXC_EPDC
1091 void epdc_clock_enable(void)
1093 clock_enable(CCGR_EPDC, 1);
1095 void epdc_clock_disable(void)
1097 clock_enable(CCGR_EPDC, 0);
1101 #ifndef CONFIG_SPL_BUILD
1103 * Dump some core clockes.
1105 int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
1109 freq = decode_pll(PLL_CORE, MXC_HCLK);
1110 printf("PLL_CORE %8d MHz\n", freq / 1000000);
1111 freq = decode_pll(PLL_SYS, MXC_HCLK);
1112 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1113 freq = decode_pll(PLL_ENET, MXC_HCLK);
1114 printf("PLL_NET %8d MHz\n", freq / 1000000);
1118 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1119 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1120 #ifdef CONFIG_MXC_SPI
1121 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1123 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1124 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1125 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1126 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1127 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1128 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1134 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,