1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <linux/types.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/types.h>
18 #if defined(CONFIG_MX6_DDRCAL)
19 static void reset_read_data_fifos(void)
21 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
23 /* Reset data FIFOs twice. */
24 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
25 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
27 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
28 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
31 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
33 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
36 * Issue the Precharge-All command to the DDR device for both
37 * chip selects. Note, CON_REQ bit should also remain set. If
38 * only using one chip select, then precharge only the desired
41 if (cs0_enable) { /* CS0 */
42 writel(0x04008050, &mmdc0->mdscr);
43 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
46 if (cs1_enable) { /* CS1 */
47 writel(0x04008058, &mmdc0->mdscr);
48 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
52 static void force_delay_measurement(int bus_size)
54 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
55 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
57 writel(0x800, &mmdc0->mpmur0);
59 writel(0x800, &mmdc1->mpmur0);
62 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
64 u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
67 * DQS gating absolute offset should be modified from reflecting
68 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
71 val_ctrl = readl(reg_ctrl);
72 val_ctrl &= 0xf0000000;
74 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
75 dg_dl_abs_offset = dg_tmp_val & 0x7f;
76 dg_hc_del = (dg_tmp_val & 0x780) << 1;
78 val_ctrl |= dg_dl_abs_offset + dg_hc_del;
80 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
81 dg_dl_abs_offset = dg_tmp_val & 0x7f;
82 dg_hc_del = (dg_tmp_val & 0x780) << 1;
84 val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
86 writel(val_ctrl, reg_ctrl);
89 static void correct_mpwldectr_result(void *reg)
91 /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
92 const unsigned int limit = 0x148;
96 if ((val & 0x17f) > limit)
99 if (((val >> 16) & 0x17f) > limit)
106 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
108 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
109 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
110 u32 esdmisc_val, zq_val;
112 u32 ldectrl[4] = {0};
117 * Stash old values in case calibration fails,
118 * we need to restore them
120 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
121 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
122 if (sysinfo->dsize == 2) {
123 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
124 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
127 /* disable DDR logic power down timer */
128 clrbits_le32(&mmdc0->mdpdc, 0xff00);
130 /* disable Adopt power down timer */
131 setbits_le32(&mmdc0->mapsr, 0x1);
133 debug("Starting write leveling calibration.\n");
136 * 2. disable auto refresh and ZQ calibration
137 * before proceeding with Write Leveling calibration
139 esdmisc_val = readl(&mmdc0->mdref);
140 writel(0x0000C000, &mmdc0->mdref);
141 zq_val = readl(&mmdc0->mpzqhwctrl);
142 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
144 /* 3. increase walat and ralat to maximum */
145 rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
146 setbits_le32(&mmdc0->mdmisc, rwalat_max);
147 if (sysinfo->dsize == 2)
148 setbits_le32(&mmdc1->mdmisc, rwalat_max);
150 * 4 & 5. Configure the external DDR device to enter write-leveling
151 * mode through Load Mode Register command.
153 * Bits[31:16] MR1 value (0x0080 write leveling enable)
154 * Bit[9] set WL_EN to enable MMDC DQS output
155 * Bits[6:4] set CMD bits for Load Mode Register programming
156 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
158 writel(0x00808231, &mmdc0->mdscr);
160 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
161 writel(0x00000001, &mmdc0->mpwlgcr);
164 * 7. Upon completion of this process the MMDC de-asserts
165 * the MPWLGCR[HW_WL_EN]
167 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
170 * 8. check for any errors: check both PHYs for x64 configuration,
171 * if x32, check only PHY0
173 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
175 if (sysinfo->dsize == 2)
176 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
179 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
181 /* check to see if cal failed */
182 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
183 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
184 ((sysinfo->dsize < 2) ||
185 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
186 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
187 debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
188 writel(ldectrl[0], &mmdc0->mpwldectrl0);
189 writel(ldectrl[1], &mmdc0->mpwldectrl1);
190 if (sysinfo->dsize == 2) {
191 writel(ldectrl[2], &mmdc1->mpwldectrl0);
192 writel(ldectrl[3], &mmdc1->mpwldectrl1);
197 correct_mpwldectr_result(&mmdc0->mpwldectrl0);
198 correct_mpwldectr_result(&mmdc0->mpwldectrl1);
199 if (sysinfo->dsize == 2) {
200 correct_mpwldectr_result(&mmdc1->mpwldectrl0);
201 correct_mpwldectr_result(&mmdc1->mpwldectrl1);
205 * User should issue MRS command to exit write leveling mode
206 * through Load Mode Register command
208 * Bits[31:16] MR1 value "ddr_mr1" value from initialization
209 * Bit[9] clear WL_EN to disable MMDC DQS output
210 * Bits[6:4] set CMD bits for Load Mode Register programming
211 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
213 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
215 /* re-enable auto refresh and zq cal */
216 writel(esdmisc_val, &mmdc0->mdref);
217 writel(zq_val, &mmdc0->mpzqhwctrl);
219 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
220 readl(&mmdc0->mpwldectrl0));
221 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
222 readl(&mmdc0->mpwldectrl1));
223 if (sysinfo->dsize == 2) {
224 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
225 readl(&mmdc1->mpwldectrl0));
226 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
227 readl(&mmdc1->mpwldectrl1));
230 /* We must force a readback of these values, to get them to stick */
231 readl(&mmdc0->mpwldectrl0);
232 readl(&mmdc0->mpwldectrl1);
233 if (sysinfo->dsize == 2) {
234 readl(&mmdc1->mpwldectrl0);
235 readl(&mmdc1->mpwldectrl1);
238 /* enable DDR logic power down timer: */
239 setbits_le32(&mmdc0->mdpdc, 0x00005500);
241 /* Enable Adopt power down timer: */
242 clrbits_le32(&mmdc0->mapsr, 0x1);
245 writel(0, &mmdc0->mdscr);
250 static void mmdc_set_sdqs(bool set)
252 struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
253 (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
254 struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
255 (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
260 sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
263 sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
267 for (i = 0; i < sdqs_cnt; i++) {
269 setbits_le32(sdqs + (4 * i), 0x7000);
271 clrbits_le32(sdqs + (4 * i), 0x7000);
275 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
277 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
278 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
281 bool cs0_enable_initial;
282 bool cs1_enable_initial;
285 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
287 u32 initdelay = 0x40404040;
289 /* check to see which chip selects are enabled */
290 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
291 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
293 /* disable DDR logic power down timer: */
294 clrbits_le32(&mmdc0->mdpdc, 0xff00);
296 /* disable Adopt power down timer: */
297 setbits_le32(&mmdc0->mapsr, 0x1);
299 /* set DQS pull ups */
302 /* Save old RALAT and WALAT values */
303 esdmisc_val = readl(&mmdc0->mdmisc);
305 setbits_le32(&mmdc0->mdmisc,
306 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
308 /* Disable auto refresh before proceeding with calibration */
309 temp_ref = readl(&mmdc0->mdref);
310 writel(0x0000c000, &mmdc0->mdref);
313 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
314 * this also sets the CON_REQ bit.
316 if (cs0_enable_initial)
317 writel(0x00008020, &mmdc0->mdscr);
318 if (cs1_enable_initial)
319 writel(0x00008028, &mmdc0->mdscr);
321 /* poll to make sure the con_ack bit was asserted */
322 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
325 * Check MDMISC register CALIB_PER_CS to see which CS calibration
326 * is targeted to (under normal cases, it should be cleared
327 * as this is the default value, indicating calibration is directed
329 * Disable the other chip select not being target for calibration
330 * to avoid any potential issues. This will get re-enabled at end
333 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
334 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
336 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
339 * Check to see which chip selects are now enabled for
340 * the remainder of the calibration.
342 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
343 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
345 precharge_all(cs0_enable, cs1_enable);
347 /* Write the pre-defined value into MPPDCMPR1 */
348 writel(pddword, &mmdc0->mppdcmpr1);
351 * Issue a write access to the external DDR device by setting
352 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
353 * this bit until it clears to indicate completion of the write access.
355 setbits_le32(&mmdc0->mpswdar0, 1);
356 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
358 /* Set the RD_DL_ABS# bits to their default values
359 * (will be calibrated later in the read delay-line calibration).
360 * Both PHYs for x64 configuration, if x32, do only PHY0.
362 writel(initdelay, &mmdc0->mprddlctl);
363 if (sysinfo->dsize == 0x2)
364 writel(initdelay, &mmdc1->mprddlctl);
366 /* Force a measurment, for previous delay setup to take effect. */
367 force_delay_measurement(sysinfo->dsize);
370 * ***************************
371 * Read DQS Gating calibration
372 * ***************************
374 debug("Starting Read DQS Gating calibration.\n");
377 * Reset the read data FIFOs (two resets); only need to issue reset
378 * to PHY0 since in x64 mode, the reset will also go to PHY1.
380 reset_read_data_fifos();
383 * Start the automatic read DQS gating calibration process by
384 * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
385 * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
386 * to indicate completion.
387 * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
388 * no errors were seen during calibration.
392 * Set bit 30: chooses option to wait 32 cycles instead of
393 * 16 before comparing read data.
395 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
396 if (sysinfo->dsize == 2)
397 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
399 /* Set bit 28 to start automatic read DQS gating calibration */
400 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
402 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
403 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
406 * Check to see if any errors were encountered during calibration
407 * (check MPDGCTRL0[HW_DG_ERR]).
408 * Check both PHYs for x64 configuration, if x32, check only PHY0.
410 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
413 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
416 /* now disable mpdgctrl0[DG_CMP_CYC] */
417 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
418 if (sysinfo->dsize == 2)
419 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
422 * DQS gating absolute offset should be modified from
423 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
424 * reflecting (HW_DG_UPx - 0x80)
426 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
428 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
430 if (sysinfo->dsize == 0x2) {
431 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
433 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
436 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
439 * **********************
440 * Read Delay calibration
441 * **********************
443 debug("Starting Read Delay calibration.\n");
445 reset_read_data_fifos();
448 * 4. Issue the Precharge-All command to the DDR device for both
449 * chip selects. If only using one chip select, then precharge
450 * only the desired chip select.
452 precharge_all(cs0_enable, cs1_enable);
455 * 9. Read delay-line calibration
456 * Start the automatic read calibration process by asserting
457 * MPRDDLHWCTL[HW_RD_DL_EN].
459 writel(0x00000030, &mmdc0->mprddlhwctl);
462 * 10. poll for completion
463 * MMDC indicates that the write data calibration had finished by
464 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
465 * no error bits were set.
467 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
469 /* check both PHYs for x64 configuration, if x32, check only PHY0 */
470 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
473 if ((sysinfo->dsize == 0x2) &&
474 (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
477 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
480 * ***********************
481 * Write Delay Calibration
482 * ***********************
484 debug("Starting Write Delay calibration.\n");
486 reset_read_data_fifos();
489 * 4. Issue the Precharge-All command to the DDR device for both
490 * chip selects. If only using one chip select, then precharge
491 * only the desired chip select.
493 precharge_all(cs0_enable, cs1_enable);
496 * 8. Set the WR_DL_ABS# bits to their default values.
497 * Both PHYs for x64 configuration, if x32, do only PHY0.
499 writel(initdelay, &mmdc0->mpwrdlctl);
500 if (sysinfo->dsize == 0x2)
501 writel(initdelay, &mmdc1->mpwrdlctl);
504 * XXX This isn't in the manual. Force a measurement,
505 * for previous delay setup to effect.
507 force_delay_measurement(sysinfo->dsize);
510 * 9. 10. Start the automatic write calibration process
511 * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
513 writel(0x00000030, &mmdc0->mpwrdlhwctl);
516 * Poll for completion.
517 * MMDC indicates that the write data calibration had finished
518 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
519 * Also, ensure that no error bits were set.
521 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
523 /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
524 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
527 if ((sysinfo->dsize == 0x2) &&
528 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
531 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
533 reset_read_data_fifos();
535 /* Enable DDR logic power down timer */
536 setbits_le32(&mmdc0->mdpdc, 0x00005500);
538 /* Enable Adopt power down timer */
539 clrbits_le32(&mmdc0->mapsr, 0x1);
541 /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
542 writel(esdmisc_val, &mmdc0->mdmisc);
544 /* Clear DQS pull ups */
545 mmdc_set_sdqs(false);
547 /* Re-enable SDE (chip selects) if they were set initially */
548 if (cs1_enable_initial)
550 setbits_le32(&mmdc0->mdctl, 1 << 30);
552 if (cs0_enable_initial)
554 setbits_le32(&mmdc0->mdctl, 1 << 31);
556 /* Re-enable to auto refresh */
557 writel(temp_ref, &mmdc0->mdref);
559 /* Clear the MDSCR (including the con_req bit) */
560 writel(0x0, &mmdc0->mdscr); /* CS0 */
562 /* Poll to make sure the con_ack bit is clear */
563 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
566 * Print out the registers that were updated as a result
567 * of the calibration process.
569 debug("MMDC registers updated from calibration\n");
570 debug("Read DQS gating calibration:\n");
571 debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
572 debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
573 if (sysinfo->dsize == 2) {
574 debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
575 debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
577 debug("Read calibration:\n");
578 debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
579 if (sysinfo->dsize == 2)
580 debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
581 debug("Write calibration:\n");
582 debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
583 if (sysinfo->dsize == 2)
584 debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
587 * Registers below are for debugging purposes. These print out
588 * the upper and lower boundaries captured during
589 * read DQS gating calibration.
591 debug("Status registers bounds for read DQS gating:\n");
592 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
593 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
594 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
595 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
596 if (sysinfo->dsize == 2) {
597 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
598 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
599 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
600 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
603 debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
609 #if defined(CONFIG_MX6SX)
610 /* Configure MX6SX mmdc iomux */
611 void mx6sx_dram_iocfg(unsigned width,
612 const struct mx6sx_iomux_ddr_regs *ddr,
613 const struct mx6sx_iomux_grp_regs *grp)
615 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
616 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
618 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
619 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
622 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
623 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
626 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
629 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
630 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
631 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
634 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
635 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
636 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
637 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
638 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
639 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
640 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
643 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
644 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
645 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
647 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
648 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
652 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
653 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
654 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
656 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
657 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
659 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
660 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
662 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
663 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
668 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
669 void mx6ul_dram_iocfg(unsigned width,
670 const struct mx6ul_iomux_ddr_regs *ddr,
671 const struct mx6ul_iomux_grp_regs *grp)
673 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
674 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
676 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
677 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
680 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
681 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
684 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
687 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
688 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
689 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
692 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
693 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
694 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
695 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
696 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
699 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
700 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
701 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
704 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
705 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
706 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
707 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
708 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
712 #if defined(CONFIG_MX6SL)
713 void mx6sl_dram_iocfg(unsigned width,
714 const struct mx6sl_iomux_ddr_regs *ddr,
715 const struct mx6sl_iomux_grp_regs *grp)
717 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
718 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
720 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
721 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
724 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
725 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
728 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
731 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
732 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
733 mx6_grp_iomux->grp_addds = grp->grp_addds;
736 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
737 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
738 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
741 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
742 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
743 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
745 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
746 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
750 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
751 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
752 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
754 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
755 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
758 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
759 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
761 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
762 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
767 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
768 /* Configure MX6DQ mmdc iomux */
769 void mx6dq_dram_iocfg(unsigned width,
770 const struct mx6dq_iomux_ddr_regs *ddr,
771 const struct mx6dq_iomux_grp_regs *grp)
773 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
774 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
776 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
777 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
780 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
781 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
784 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
785 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
788 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
789 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
790 mx6_grp_iomux->grp_addds = grp->grp_addds;
793 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
794 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
795 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
796 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
797 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
798 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
799 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
802 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
803 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
804 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
806 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
807 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
810 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
811 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
812 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
813 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
817 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
818 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
819 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
821 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
822 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
825 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
826 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
827 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
828 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
830 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
831 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
833 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
834 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
837 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
838 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
839 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
840 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
845 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
846 /* Configure MX6SDL mmdc iomux */
847 void mx6sdl_dram_iocfg(unsigned width,
848 const struct mx6sdl_iomux_ddr_regs *ddr,
849 const struct mx6sdl_iomux_grp_regs *grp)
851 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
852 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
854 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
855 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
858 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
859 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
862 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
863 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
866 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
867 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
868 mx6_grp_iomux->grp_addds = grp->grp_addds;
871 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
872 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
873 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
874 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
875 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
876 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
877 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
880 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
881 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
882 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
884 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
885 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
888 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
889 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
890 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
891 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
895 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
896 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
897 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
899 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
900 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
903 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
904 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
905 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
906 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
908 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
909 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
911 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
912 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
915 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
916 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
917 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
918 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
924 * Configure mx6 mmdc registers based on:
925 * - board-specific memory configuration
926 * - board-specific calibration data
927 * - ddr3/lpddr2 chip details
929 * The various calculations here are derived from the Freescale
930 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
931 * MMDC configuration registers based on memory system and memory chip
934 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
935 * configuration registers based on memory system and memory chip
938 * The defaults here are those which were specified in the spreadsheet.
939 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
940 * and/or IMX6SLRM section titled MMDC initialization.
942 #define MR(val, ba, cmd, cs1) \
943 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
944 #define MMDC1(entry, value) do { \
945 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
946 mmdc1->entry = value; \
949 /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
950 #define BOOT_CFG3_DDR_MASK 0x30
951 #define BOOT_CFG3_EXT_DDR_MASK 0x33
953 #define DDR_MMAP_NOC_SINGLE 0
954 #define DDR_MMAP_NOC_DUAL 0x31
956 /* NoC ACTIVATE shifts */
957 #define NOC_RD_SHIFT 0
958 #define NOC_FAW_PERIOD_SHIFT 4
959 #define NOC_FAW_BANKS_SHIFT 10
961 /* NoC DdrTiming shifts */
962 #define NOC_ACT_TO_ACT_SHIFT 0
963 #define NOC_RD_TO_MISS_SHIFT 6
964 #define NOC_WR_TO_MISS_SHIFT 12
965 #define NOC_BURST_LEN_SHIFT 18
966 #define NOC_RD_TO_WR_SHIFT 21
967 #define NOC_WR_TO_RD_SHIFT 26
968 #define NOC_BW_RATIO_SHIFT 31
971 * According JESD209-2B-LPDDR2: Table 103
974 static int lpddr2_wl(uint32_t mem_speed)
989 puts("invalid memory speed\n");
997 * According JESD209-2B-LPDDR2: Table 103
1000 static int lpddr2_rl(uint32_t mem_speed)
1002 switch (mem_speed) {
1017 puts("invalid memory speed\n");
1024 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1025 const struct mx6_mmdc_calibration *calib,
1026 const struct mx6_lpddr2_cfg *lpddr2_cfg)
1028 volatile struct mmdc_p_regs *mmdc0;
1030 u8 tcke, tcksrx, tcksre, trrd;
1031 u8 twl, txp, tfaw, tcl;
1032 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
1033 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
1036 int clkper; /* clock period in picoseconds */
1037 int clock; /* clock freq in mHz */
1040 /* only support 16/32 bits */
1041 if (sysinfo->dsize > 1)
1044 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1046 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
1047 clkper = (1000 * 1000) / clock; /* pico seconds */
1049 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
1051 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
1052 switch (lpddr2_cfg->density) {
1056 trfc = DIV_ROUND_UP(130000, clkper) - 1;
1057 txsr = DIV_ROUND_UP(140000, clkper) - 1;
1060 trfc = DIV_ROUND_UP(210000, clkper) - 1;
1061 txsr = DIV_ROUND_UP(220000, clkper) - 1;
1065 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
1071 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
1073 txp = DIV_ROUND_UP(7500, clkper) - 1;
1075 if (lpddr2_cfg->mem_speed == 333)
1076 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
1078 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1079 trrd = DIV_ROUND_UP(10000, clkper) - 1;
1081 /* tckesr for LPDDR2 */
1082 tcksre = DIV_ROUND_UP(15000, clkper);
1084 twr = DIV_ROUND_UP(15000, clkper) - 1;
1087 * tMRD should be set to max(tMRR, tMRW)
1090 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
1091 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
1092 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
1093 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
1095 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
1096 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
1097 /* To LPDDR2, CL in MDCFG0 refers to RL */
1098 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
1099 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1100 trtp = DIV_ROUND_UP(7500, clkper) - 1;
1102 cs0_end = 4 * sysinfo->cs_density - 1;
1104 debug("density:%d Gb (%d Gb per chip)\n",
1105 sysinfo->cs_density, lpddr2_cfg->density);
1106 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1107 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
1108 debug("trcd_lp=%d\n", trcd_lp);
1109 debug("trppb_lp=%d\n", trppb_lp);
1110 debug("trpab_lp=%d\n", trpab_lp);
1111 debug("trc_lp=%d\n", trc_lp);
1112 debug("tcke=%d\n", tcke);
1113 debug("tcksrx=%d\n", tcksrx);
1114 debug("tcksre=%d\n", tcksre);
1115 debug("trfc=%d\n", trfc);
1116 debug("txsr=%d\n", txsr);
1117 debug("txp=%d\n", txp);
1118 debug("tfaw=%d\n", tfaw);
1119 debug("tcl=%d\n", tcl);
1120 debug("tras=%d\n", tras);
1121 debug("twr=%d\n", twr);
1122 debug("tmrd=%d\n", tmrd);
1123 debug("twl=%d\n", twl);
1124 debug("trtp=%d\n", trtp);
1125 debug("twtr=%d\n", twtr);
1126 debug("trrd=%d\n", trrd);
1127 debug("cs0_end=%d\n", cs0_end);
1128 debug("ncs=%d\n", sysinfo->ncs);
1131 * board-specific configuration:
1132 * These values are determined empirically and vary per board layout
1134 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1135 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1136 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1137 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1138 mmdc0->mprddlctl = calib->p0_mprddlctl;
1139 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1140 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1142 /* Read data DQ Byte0-3 delay */
1143 mmdc0->mprddqby0dl = 0x33333333;
1144 mmdc0->mprddqby1dl = 0x33333333;
1145 if (sysinfo->dsize > 0) {
1146 mmdc0->mprddqby2dl = 0x33333333;
1147 mmdc0->mprddqby3dl = 0x33333333;
1150 /* Write data DQ Byte0-3 delay */
1151 mmdc0->mpwrdqby0dl = 0xf3333333;
1152 mmdc0->mpwrdqby1dl = 0xf3333333;
1153 if (sysinfo->dsize > 0) {
1154 mmdc0->mpwrdqby2dl = 0xf3333333;
1155 mmdc0->mpwrdqby3dl = 0xf3333333;
1159 * In LPDDR2 mode this register should be cleared,
1160 * so no termination will be activated.
1162 mmdc0->mpodtctrl = 0;
1164 /* complete calibration */
1165 val = (1 << 11); /* Force measurement on delay-lines */
1166 mmdc0->mpmur0 = val;
1168 /* Step 1: configuration request */
1169 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1171 /* Step 2: Timing configuration */
1172 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1174 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1175 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1176 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1177 (trppb_lp << 4) | trpab_lp;
1180 mmdc0->mdasp = cs0_end; /* CS addressing */
1182 /* Step 3: Configure DDR type */
1183 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1184 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1185 (sysinfo->ralat << 6) | (1 << 3);
1187 /* Step 4: Configure delay while leaving reset */
1188 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1189 (sysinfo->rst_to_cke << 0);
1191 /* Step 5: Configure DDR physical parameters (density and burst len) */
1192 coladdr = lpddr2_cfg->coladdr;
1193 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1195 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1197 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1198 (coladdr - 9) << 20 | /* COL */
1199 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
1200 (sysinfo->dsize << 16); /* DDR data bus size */
1202 /* Step 6: Perform ZQ calibration */
1203 val = 0xa1390003; /* one-time HW ZQ calib */
1204 mmdc0->mpzqhwctrl = val;
1206 /* Step 7: Enable MMDC with desired chip select */
1207 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1208 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1210 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
1211 for (cs = 0; cs < sysinfo->ncs; cs++) {
1213 mmdc0->mdscr = MR(63, 0, 3, cs);
1214 /* MR10: calibration,
1215 * 0xff is calibration command after intilization.
1217 val = 0xA | (0xff << 8);
1218 mmdc0->mdscr = MR(val, 0, 3, cs);
1220 val = 0x1 | (0x82 << 8);
1221 mmdc0->mdscr = MR(val, 0, 3, cs);
1223 val = 0x2 | (0x04 << 8);
1224 mmdc0->mdscr = MR(val, 0, 3, cs);
1226 val = 0x3 | (0x02 << 8);
1227 mmdc0->mdscr = MR(val, 0, 3, cs);
1230 /* Step 10: Power down control and self-refresh */
1231 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1232 5 << 12 | /* PWDT_1: 256 cycles */
1233 5 << 8 | /* PWDT_0: 256 cycles */
1234 1 << 6 | /* BOTH_CS_PD */
1235 (tcksrx & 0x7) << 3 |
1237 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1239 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1241 mmdc0->mpzqhwctrl = val;
1243 /* Step 12: Configure and activate periodic refresh */
1244 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1246 /* Step 13: Deassert config request - init complete */
1247 mmdc0->mdscr = 0x00000000;
1249 /* wait for auto-ZQ calibration to complete */
1253 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1254 const struct mx6_mmdc_calibration *calib,
1255 const struct mx6_ddr3_cfg *ddr3_cfg)
1257 volatile struct mmdc_p_regs *mmdc0;
1258 volatile struct mmdc_p_regs *mmdc1;
1259 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
1260 u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
1262 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
1263 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
1264 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
1265 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
1267 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
1269 int clkper; /* clock period in picoseconds */
1270 int clock; /* clock freq in MHz */
1272 u16 mem_speed = ddr3_cfg->mem_speed;
1274 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1275 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
1276 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1278 /* Limit mem_speed for MX6D/MX6Q */
1279 if (is_mx6dq() || is_mx6dqp()) {
1280 if (mem_speed > 1066)
1281 mem_speed = 1066; /* 1066 MT/s */
1285 /* Limit mem_speed for MX6S/MX6DL */
1287 if (mem_speed > 800)
1288 mem_speed = 800; /* 800 MT/s */
1293 clock = mem_speed / 2;
1295 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1296 * up to 528 MHz, so reduce the clock to fit chip specs
1298 if (is_mx6dq() || is_mx6dqp()) {
1300 clock = 528; /* 528 MHz */
1303 clkper = (1000 * 1000) / clock; /* pico seconds */
1308 switch (ddr3_cfg->density) {
1309 case 1: /* 1Gb per chip */
1310 trfc = DIV_ROUND_UP(110000, clkper) - 1;
1311 txs = DIV_ROUND_UP(120000, clkper) - 1;
1313 case 2: /* 2Gb per chip */
1314 trfc = DIV_ROUND_UP(160000, clkper) - 1;
1315 txs = DIV_ROUND_UP(170000, clkper) - 1;
1317 case 4: /* 4Gb per chip */
1318 trfc = DIV_ROUND_UP(260000, clkper) - 1;
1319 txs = DIV_ROUND_UP(270000, clkper) - 1;
1321 case 8: /* 8Gb per chip */
1322 trfc = DIV_ROUND_UP(350000, clkper) - 1;
1323 txs = DIV_ROUND_UP(360000, clkper) - 1;
1326 /* invalid density */
1327 puts("invalid chip density\n");
1333 switch (mem_speed) {
1335 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1336 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1337 if (ddr3_cfg->pagesz == 1) {
1338 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
1339 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1341 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1342 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1346 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1347 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
1348 if (ddr3_cfg->pagesz == 1) {
1349 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
1350 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
1352 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1353 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1357 puts("invalid memory speed\n");
1361 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
1362 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
1363 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
1366 twr = DIV_ROUND_UP(15000, clkper) - 1;
1367 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
1368 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
1369 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
1370 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
1371 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
1372 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1375 cs0_end = 4 * sysinfo->cs_density - 1;
1377 debug("density:%d Gb (%d Gb per chip)\n",
1378 sysinfo->cs_density, ddr3_cfg->density);
1379 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1380 debug("memspd:%d\n", mem_speed);
1381 debug("tcke=%d\n", tcke);
1382 debug("tcksrx=%d\n", tcksrx);
1383 debug("tcksre=%d\n", tcksre);
1384 debug("taofpd=%d\n", taofpd);
1385 debug("taonpd=%d\n", taonpd);
1386 debug("todtlon=%d\n", todtlon);
1387 debug("tanpd=%d\n", tanpd);
1388 debug("taxpd=%d\n", taxpd);
1389 debug("trfc=%d\n", trfc);
1390 debug("txs=%d\n", txs);
1391 debug("txp=%d\n", txp);
1392 debug("txpdll=%d\n", txpdll);
1393 debug("tfaw=%d\n", tfaw);
1394 debug("tcl=%d\n", tcl);
1395 debug("trcd=%d\n", trcd);
1396 debug("trp=%d\n", trp);
1397 debug("trc=%d\n", trc);
1398 debug("tras=%d\n", tras);
1399 debug("twr=%d\n", twr);
1400 debug("tmrd=%d\n", tmrd);
1401 debug("tcwl=%d\n", tcwl);
1402 debug("tdllk=%d\n", tdllk);
1403 debug("trtp=%d\n", trtp);
1404 debug("twtr=%d\n", twtr);
1405 debug("trrd=%d\n", trrd);
1406 debug("txpr=%d\n", txpr);
1407 debug("cs0_end=%d\n", cs0_end);
1408 debug("ncs=%d\n", sysinfo->ncs);
1409 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
1410 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
1411 debug("SRT=%d\n", ddr3_cfg->SRT);
1412 debug("twr=%d\n", twr);
1415 * board-specific configuration:
1416 * These values are determined empirically and vary per board layout
1418 * appnote, ddr3 spreadsheet
1420 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1421 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1422 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1423 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1424 mmdc0->mprddlctl = calib->p0_mprddlctl;
1425 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1426 if (sysinfo->dsize > 1) {
1427 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1428 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1429 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1430 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1431 MMDC1(mprddlctl, calib->p1_mprddlctl);
1432 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1435 /* Read data DQ Byte0-3 delay */
1436 mmdc0->mprddqby0dl = 0x33333333;
1437 mmdc0->mprddqby1dl = 0x33333333;
1438 if (sysinfo->dsize > 0) {
1439 mmdc0->mprddqby2dl = 0x33333333;
1440 mmdc0->mprddqby3dl = 0x33333333;
1443 if (sysinfo->dsize > 1) {
1444 MMDC1(mprddqby0dl, 0x33333333);
1445 MMDC1(mprddqby1dl, 0x33333333);
1446 MMDC1(mprddqby2dl, 0x33333333);
1447 MMDC1(mprddqby3dl, 0x33333333);
1450 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
1451 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
1452 mmdc0->mpodtctrl = val;
1453 if (sysinfo->dsize > 1)
1454 MMDC1(mpodtctrl, val);
1456 /* complete calibration */
1457 val = (1 << 11); /* Force measurement on delay-lines */
1458 mmdc0->mpmur0 = val;
1459 if (sysinfo->dsize > 1)
1462 /* Step 1: configuration request */
1463 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1465 /* Step 2: Timing configuration */
1466 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1467 (txpdll << 9) | (tfaw << 4) | tcl;
1468 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1469 (tras << 16) | (1 << 15) /* trpa */ |
1470 (twr << 9) | (tmrd << 5) | tcwl;
1471 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1472 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1473 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
1474 mmdc0->mdasp = cs0_end; /* CS addressing */
1476 /* Step 3: Configure DDR type */
1477 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1478 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1479 (sysinfo->ralat << 6);
1481 /* Step 4: Configure delay while leaving reset */
1482 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1483 (sysinfo->rst_to_cke << 0);
1485 /* Step 5: Configure DDR physical parameters (density and burst len) */
1486 coladdr = ddr3_cfg->coladdr;
1487 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1489 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1491 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1492 (coladdr - 9) << 20 | /* COL */
1493 (1 << 19) | /* Burst Length = 8 for DDR3 */
1494 (sysinfo->dsize << 16); /* DDR data bus size */
1496 /* Step 6: Perform ZQ calibration */
1497 val = 0xa1390001; /* one-time HW ZQ calib */
1498 mmdc0->mpzqhwctrl = val;
1499 if (sysinfo->dsize > 1)
1500 MMDC1(mpzqhwctrl, val);
1502 /* Step 7: Enable MMDC with desired chip select */
1503 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1504 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1506 /* Step 8: Write Mode Registers to Init DDR3 devices */
1507 for (cs = 0; cs < sysinfo->ncs; cs++) {
1509 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
1510 ((tcwl - 3) & 3) << 3;
1511 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
1512 mmdc0->mdscr = MR(val, 2, 3, cs);
1514 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
1515 mmdc0->mdscr = MR(0, 3, 3, cs);
1517 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
1518 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
1519 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
1520 mmdc0->mdscr = MR(val, 1, 3, cs);
1522 val = ((tcl - 1) << 4) | /* CAS */
1523 (1 << 8) | /* DLL Reset */
1524 ((twr - 3) << 9) | /* Write Recovery */
1525 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
1526 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
1527 mmdc0->mdscr = MR(val, 0, 3, cs);
1528 /* ZQ calibration */
1530 mmdc0->mdscr = MR(val, 0, 4, cs);
1533 /* Step 10: Power down control and self-refresh */
1534 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1535 5 << 12 | /* PWDT_1: 256 cycles */
1536 5 << 8 | /* PWDT_0: 256 cycles */
1537 1 << 6 | /* BOTH_CS_PD */
1538 (tcksrx & 0x7) << 3 |
1540 if (!sysinfo->pd_fast_exit)
1541 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1542 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1544 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1546 mmdc0->mpzqhwctrl = val;
1547 if (sysinfo->dsize > 1)
1548 MMDC1(mpzqhwctrl, val);
1550 /* Step 12: Configure and activate periodic refresh */
1551 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1554 * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
1555 * configure it and disable MMDC arbitration/reordering (see EB828)
1558 ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
1559 (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
1560 struct mx6dqp_noc_sched_regs *noc_sched =
1561 (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
1564 * These values are fixed based on integration parameters and
1565 * should not be modified
1567 noc_sched->rlat = 0x00000040;
1568 noc_sched->ipu1 = 0x00000020;
1569 noc_sched->ipu2 = 0x00000020;
1571 noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
1572 (tfaw << NOC_FAW_PERIOD_SHIFT) |
1573 (trrd << NOC_RD_SHIFT);
1574 noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
1575 << NOC_BW_RATIO_SHIFT) |
1576 ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
1577 ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
1578 (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
1579 ((tcwl + twr + trp + trcd)
1580 << NOC_WR_TO_MISS_SHIFT) |
1581 ((trtp + trp + trcd - 4)
1582 << NOC_RD_TO_MISS_SHIFT) |
1583 (trc << NOC_ACT_TO_ACT_SHIFT);
1585 if (sysinfo->dsize == 2) {
1586 if (ddr3_cfg->coladdr == 10) {
1587 if (ddr3_cfg->rowaddr == 15 &&
1589 noc_sched->ddrconf = 4;
1591 noc_sched->ddrconf = 0;
1592 } else if (ddr3_cfg->coladdr == 11) {
1593 noc_sched->ddrconf = 1;
1596 if (ddr3_cfg->coladdr == 9) {
1597 if (ddr3_cfg->rowaddr == 13)
1598 noc_sched->ddrconf = 2;
1599 else if (ddr3_cfg->rowaddr == 14)
1600 noc_sched->ddrconf = 15;
1601 } else if (ddr3_cfg->coladdr == 10) {
1602 if (ddr3_cfg->rowaddr == 14 &&
1604 noc_sched->ddrconf = 14;
1605 else if (ddr3_cfg->rowaddr == 15 &&
1607 noc_sched->ddrconf = 9;
1609 noc_sched->ddrconf = 3;
1610 } else if (ddr3_cfg->coladdr == 11) {
1611 if (ddr3_cfg->rowaddr == 15 &&
1613 noc_sched->ddrconf = 4;
1615 noc_sched->ddrconf = 0;
1616 } else if (ddr3_cfg->coladdr == 12) {
1617 if (ddr3_cfg->rowaddr == 14)
1618 noc_sched->ddrconf = 1;
1622 /* Disable MMDC arbitration/reordering */
1623 mmdc0->maarcr = 0x14420000;
1626 /* Step 13: Deassert config request - init complete */
1627 mmdc0->mdscr = 0x00000000;
1629 /* wait for auto-ZQ calibration to complete */
1633 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
1634 struct mx6_mmdc_calibration *calib)
1636 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1637 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1639 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
1640 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
1641 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
1642 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
1643 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
1644 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
1646 if (sysinfo->dsize == 2) {
1647 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
1648 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
1649 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
1650 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
1651 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
1652 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
1656 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1657 const struct mx6_mmdc_calibration *calib,
1658 const void *ddr_cfg)
1660 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
1661 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
1662 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
1663 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
1665 puts("Unsupported ddr type\n");