1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Stefan Roese <sr@denx.de>
9 #include <asm/arch/sys_proto.h>
10 #include <linux/delay.h>
11 #include <linux/errno.h>
13 #include <asm/mach-imx/regs-common.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 /* 1 second delay should be plenty of time for block reset. */
18 #define RESET_MAX_TIMEOUT 1000000
20 #define MXS_BLOCK_SFTRST (1 << 31)
21 #define MXS_BLOCK_CLKGATE (1 << 30)
23 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
27 if ((readl(®->reg) & mask) == mask)
35 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
39 if ((readl(®->reg) & mask) == 0)
47 int mxs_reset_block(struct mxs_register_32 *reg)
50 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
52 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
56 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
59 writel(MXS_BLOCK_SFTRST, ®->reg_set);
61 /* Wait for CLKGATE being set */
62 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
66 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
68 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
72 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
74 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
80 static ulong get_sp(void)
84 asm("mov %0, sp" : "=r"(ret) : );
88 void board_lmb_reserve(struct lmb *lmb)
94 debug("## Current stack ends at 0x%08lx ", sp);
96 /* adjust sp by 16K to be safe */
98 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
99 if (sp < gd->bd->bi_dram[bank].start)
101 bank_end = gd->bd->bi_dram[bank].start +
102 gd->bd->bi_dram[bank].size;
105 lmb_reserve(lmb, sp, bank_end - sp);