1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Stefan Roese <sr@denx.de>
7 #include <asm/arch/sys_proto.h>
8 #include <linux/errno.h>
10 #include <asm/mach-imx/regs-common.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 /* 1 second delay should be plenty of time for block reset. */
15 #define RESET_MAX_TIMEOUT 1000000
17 #define MXS_BLOCK_SFTRST (1 << 31)
18 #define MXS_BLOCK_CLKGATE (1 << 30)
20 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
24 if ((readl(®->reg) & mask) == mask)
32 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
36 if ((readl(®->reg) & mask) == 0)
44 int mxs_reset_block(struct mxs_register_32 *reg)
47 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
49 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
53 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
56 writel(MXS_BLOCK_SFTRST, ®->reg_set);
58 /* Wait for CLKGATE being set */
59 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
63 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
65 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
69 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
71 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
77 static ulong get_sp(void)
81 asm("mov %0, sp" : "=r"(ret) : );
85 void board_lmb_reserve(struct lmb *lmb)
91 debug("## Current stack ends at 0x%08lx ", sp);
93 /* adjust sp by 16K to be safe */
95 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
96 if (sp < gd->bd->bi_dram[bank].start)
98 bank_end = gd->bd->bi_dram[bank].start +
99 gd->bd->bi_dram[bank].size;
102 lmb_reserve(lmb, sp, bank_end - sp);