2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
16 if (!boot_private_data)
19 stack = *(ulong *)boot_private_data;
20 pc = *(ulong *)(boot_private_data + 4);
22 /* Set the stack and pc to M4 bootROM */
23 writel(stack, M4_BOOTROM_BASE_ADDR);
24 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
27 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
28 SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
33 int arch_auxiliary_core_check_up(u32 core_id)
37 val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
39 if (val & SRC_M4C_NON_SCLR_RST_MASK)
40 return 0; /* assert in reset */
46 * To i.MX6SX and i.MX7D, the image supported by bootaux needs
47 * the reset vector at the head for the image, with SP and PC
48 * as the first two words.
50 * Per the cortex-M reference manual, the reset vector of M4 needs
51 * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
52 * of that vector. So to boot M4, the A core must build the M4's reset
53 * vector with getting the PC and SP from image and filling them to
54 * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
55 * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
56 * accessing the M4 TCMUL.
58 static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
66 up = arch_auxiliary_core_check_up(0);
68 printf("## Auxiliary core is already up\n");
69 return CMD_RET_SUCCESS;
72 addr = simple_strtoul(argv[1], NULL, 16);
74 printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
76 ret = arch_auxiliary_core_up(0, addr);
78 return CMD_RET_FAILURE;
80 return CMD_RET_SUCCESS;
84 bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
85 "Start auxiliary core",