arch/arm/mach-imx/imx9/clock.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2022 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/ccm_regs.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <div64.h>
  17 #include <errno.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20 #include <log.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
  25
  26 static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
  27         INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
  28         INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
  29         INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
  30         INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
  31         INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
  32 };
  33
  34 static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
  35         FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
  36         FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
  37         FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
  38         FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
  39         FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
  40 };
  41
  42 /* return in khz */
  43 static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll)
  44 {
  45         u32 ctrl;
  46         u32 pll_status;
  47         u32 div;
  48         int rdiv, mfi, mfn, mfd;
  49         int clk = 24000;
  50
  51         ctrl = readl(&reg->ctrl.reg);
  52         pll_status = readl(&reg->pll_status);
  53         div = readl(&reg->div.reg);
  54
  55         if (!(ctrl & PLL_CTRL_POWERUP))
  56                 return 0;
  57
  58         if (!(pll_status & PLL_STATUS_PLL_LOCK))
  59                 return 0;
  60
  61         mfi = (div & GENMASK(24, 16)) >> 16;
  62         rdiv = (div & GENMASK(15, 13)) >> 13;
  63
  64         if (rdiv == 0)
  65                 rdiv = 1;
  66
  67         if (fracpll) {
  68                 mfn = (int)readl(&reg->num.reg);
  69                 mfn >>= 2;
  70                 mfd = (int)(readl(&reg->denom.reg) & GENMASK(29, 0));
  71
  72                 clk = clk * (mfi * mfd + mfn) / mfd / rdiv;
  73         } else {
  74                 clk = clk * mfi / rdiv;
  75         }
  76
  77         return (u32)clk;
  78 }
  79
  80 /* return in khz */
  81 static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll)
  82 {
  83         u32 ctrl = readl(&reg->ctrl.reg);
  84         u32 div;
  85
  86         if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
  87                 return 24000;
  88
  89         if (!(ctrl & PLL_CTRL_CLKMUX_EN))
  90                 return 0;
  91
  92         div = readl(&reg->div.reg);
  93         div &= 0xff; /* odiv */
  94
  95         if (div == 0)
  96                 div = 2;
  97         else if (div == 1)
  98                 div = 3;
  99
 100         return decode_pll_vco(reg, fracpll) / div;
 101 }
 102
 103 /* return in khz */
 104 static u32 decode_pll_pfd(struct ana_pll_reg *reg, struct ana_pll_dfs *dfs_reg,
 105                           bool div2, bool fracpll)
 106 {
 107         u32 pllvco = decode_pll_vco(reg, fracpll);
 108         u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg);
 109         u32 dfs_div = readl(&dfs_reg->dfs_div.reg);
 110         u32 mfn, mfi;
 111         u32 output;
 112
 113         if (dfs_ctrl & PLL_DFS_CTRL_BYPASS)
 114                 return pllvco;
 115
 116         if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) ||
 117             (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) ||
 118             (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT)))
 119                 return 0;
 120
 121         mfn = dfs_div & GENMASK(2, 0);
 122         mfi = (dfs_div & GENMASK(15, 8)) >> 8;
 123
 124         if (mfn > 3)
 125                 return 0; /* valid mfn 0-3 */
 126
 127         if (mfi == 0 || mfi == 1)
 128                 return 0; /* valid mfi 2-255 */
 129
 130         output = (pllvco * 5) / (mfi * 5 + mfn);
 131
 132         if (div2)
 133                 return output >> 1;
 134
 135         return output;
 136 }
 137
 138 static u32 decode_pll(enum ccm_clk_src pll)
 139 {
 140         switch (pll) {
 141         case ARM_PLL_CLK:
 142                 return decode_pll_out(&ana_regs->arm_pll, false);
 143         case SYS_PLL_PG:
 144                 return decode_pll_out(&ana_regs->sys_pll, false);
 145         case SYS_PLL_PFD0:
 146                 return decode_pll_pfd(&ana_regs->sys_pll,
 147                         &ana_regs->sys_pll.dfs[0], false, true);
 148         case SYS_PLL_PFD0_DIV2:
 149                 return decode_pll_pfd(&ana_regs->sys_pll,
 150                         &ana_regs->sys_pll.dfs[0], true, true);
 151         case SYS_PLL_PFD1:
 152                 return decode_pll_pfd(&ana_regs->sys_pll,
 153                         &ana_regs->sys_pll.dfs[1], false, true);
 154         case SYS_PLL_PFD1_DIV2:
 155                 return decode_pll_pfd(&ana_regs->sys_pll,
 156                         &ana_regs->sys_pll.dfs[1], true, true);
 157         case SYS_PLL_PFD2:
 158                 return decode_pll_pfd(&ana_regs->sys_pll,
 159                         &ana_regs->sys_pll.dfs[2], false, true);
 160         case SYS_PLL_PFD2_DIV2:
 161                 return decode_pll_pfd(&ana_regs->sys_pll,
 162                         &ana_regs->sys_pll.dfs[2], true, true);
 163         case AUDIO_PLL_CLK:
 164                 return decode_pll_out(&ana_regs->audio_pll, true);
 165         case DRAM_PLL_CLK:
 166                 return decode_pll_out(&ana_regs->dram_pll, true);
 167         case VIDEO_PLL_CLK:
 168                 return decode_pll_out(&ana_regs->video_pll, true);
 169         default:
 170                 printf("Invalid clock source to decode\n");
 171                 break;
 172         }
 173
 174         return 0;
 175 }
 176
 177 int configure_intpll(enum ccm_clk_src pll, u32 freq)
 178 {
 179         int i;
 180         struct imx_intpll_rate_table *rate;
 181         struct ana_pll_reg *reg;
 182         u32 pll_status;
 183
 184         for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) {
 185                 if (freq == imx9_intpll_tbl[i].rate)
 186                         break;
 187         }
 188
 189         if (i == ARRAY_SIZE(imx9_intpll_tbl)) {
 190                 debug("No matched freq table %u\n", freq);
 191                 return -EINVAL;
 192         }
 193
 194         rate = &imx9_intpll_tbl[i];
 195
 196         /* ROM has configured SYS PLL and PFD, no need for it */
 197         switch (pll) {
 198         case ARM_PLL_CLK:
 199                 reg = &ana_regs->arm_pll;
 200                 break;
 201         default:
 202                 return -EPERM;
 203         }
 204
 205         /* Bypass the PLL to ref */
 206         writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
 207
 208         /* disable pll and output */
 209         writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
 210
 211         /* Program the ODIV, RDIV, MFI */
 212         writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
 213                ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
 214
 215         /* wait 5us */
 216         udelay(5);
 217
 218         /* power up the PLL and wait lock (max wait time 100 us) */
 219         writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
 220
 221         udelay(100);
 222
 223         pll_status = readl(&reg->pll_status);
 224         if (pll_status & PLL_STATUS_PLL_LOCK) {
 225                 writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
 226
 227                 /* clear bypass */
 228                 writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
 229
 230         } else {
 231                 debug("Fail to lock PLL %u\n", pll);
 232                 return -EIO;
 233         }
 234
 235         return 0;
 236 }
 237
 238 int configure_fracpll(enum ccm_clk_src pll, u32 freq)
 239 {
 240         struct imx_fracpll_rate_table *rate;
 241         struct ana_pll_reg *reg;
 242         u32 pll_status;
 243         int i;
 244
 245         for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
 246                 if (freq == imx9_fracpll_tbl[i].rate)
 247                         break;
 248         }
 249
 250         if (i == ARRAY_SIZE(imx9_fracpll_tbl)) {
 251                 debug("No matched freq table %u\n", freq);
 252                 return -EINVAL;
 253         }
 254
 255         rate = &imx9_fracpll_tbl[i];
 256
 257         switch (pll) {
 258         case SYS_PLL_PG:
 259                 reg = &ana_regs->sys_pll;
 260                 break;
 261         case DRAM_PLL_CLK:
 262                 reg = &ana_regs->dram_pll;
 263                 break;
 264         case VIDEO_PLL_CLK:
 265                 reg = &ana_regs->video_pll;
 266                 break;
 267         default:
 268                 return -EPERM;
 269         }
 270
 271         /* Bypass the PLL to ref */
 272         writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
 273
 274         /* disable pll and output */
 275         writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
 276
 277         /* Program the ODIV, RDIV, MFI */
 278         writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
 279                ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
 280
 281         /* Set SPREAD_SPECRUM enable to 0 */
 282         writel(PLL_SS_EN, &reg->ss.reg_clr);
 283
 284         /* Program NUMERATOR and DENOMINATOR */
 285         writel((rate->mfn << 2), &reg->num.reg);
 286         writel((rate->mfd & GENMASK(29, 0)), &reg->denom.reg);
 287
 288         /* wait 5us */
 289         udelay(5);
 290
 291         /* power up the PLL and wait lock (max wait time 100 us) */
 292         writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
 293
 294         udelay(100);
 295
 296         pll_status = readl(&reg->pll_status);
 297         if (pll_status & PLL_STATUS_PLL_LOCK) {
 298                 writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
 299
 300                 /* check the MFN is updated */
 301                 pll_status = readl(&reg->pll_status);
 302                 if ((pll_status & ~0x3) != (rate->mfn << 2)) {
 303                         debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n",
 304                               pll_status, rate->mfn);
 305                         return -EIO;
 306                 }
 307
 308                 /* clear bypass */
 309                 writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
 310
 311         } else {
 312                 debug("Fail to lock PLL %u\n", pll);
 313                 return -EIO;
 314         }
 315
 316         return 0;
 317 }
 318
 319 int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en)
 320 {
 321         struct ana_pll_dfs *dfs;
 322         struct ana_pll_reg *reg;
 323         u32 dfs_status;
 324         u32 index;
 325
 326         if (mfn > 3)
 327                 return -EINVAL; /* valid mfn 0-3 */
 328
 329         if (mfi < 2 || mfi > 255)
 330                 return -EINVAL; /* valid mfi 2-255 */
 331
 332         switch (pll_pfg) {
 333         case SYS_PLL_PFD0:
 334                 reg = &ana_regs->sys_pll;
 335                 index = 0;
 336                 break;
 337         case SYS_PLL_PFD1:
 338                 reg = &ana_regs->sys_pll;
 339                 index = 1;
 340                 break;
 341         case SYS_PLL_PFD2:
 342                 reg = &ana_regs->sys_pll;
 343                 index = 2;
 344                 break;
 345         default:
 346                 return -EPERM;
 347         }
 348
 349         dfs = &reg->dfs[index];
 350
 351         /* Bypass the DFS to PLL VCO */
 352         writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set);
 353
 354         /* disable DFS and output */
 355         writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT |
 356                 PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr);
 357
 358         writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)), &dfs->dfs_div.reg);
 359
 360         writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set);
 361         if (div2_en)
 362                 writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set);
 363         writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set);
 364
 365         /*
 366          * As HW expert said: after enabling the DFS, clock will start
 367          * coming after 6 cycles output clock period.
 368          * 5us is much bigger than expected, so it will be safe
 369          */
 370         udelay(5);
 371
 372         dfs_status = readl(&reg->dfs_status);
 373
 374         if (!(dfs_status & (1 << index))) {
 375                 debug("DFS lock failed\n");
 376                 return -EIO;
 377         }
 378
 379         /* Bypass the DFS to PLL VCO */
 380         writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr);
 381
 382         return 0;
 383 }
 384
 385 int update_fracpll_mfn(enum ccm_clk_src pll, int mfn)
 386 {
 387         struct ana_pll_reg *reg;
 388         bool repoll = false;
 389         u32 pll_status;
 390         int count = 20;
 391
 392         switch (pll) {
 393         case AUDIO_PLL_CLK:
 394                 reg = &ana_regs->audio_pll;
 395                 break;
 396         case DRAM_PLL_CLK:
 397                 reg = &ana_regs->dram_pll;
 398                 break;
 399         case VIDEO_PLL_CLK:
 400                 reg = &ana_regs->video_pll;
 401                 break;
 402         default:
 403                 printf("Invalid pll %u for update FRAC PLL MFN\n", pll);
 404                 return -EINVAL;
 405         }
 406
 407         if (readl(&reg->pll_status) & PLL_STATUS_PLL_LOCK)
 408                 repoll = true;
 409
 410         mfn <<= 2;
 411         writel(mfn, &reg->num);
 412
 413         if (repoll) {
 414                 do {
 415                         pll_status = readl(&reg->pll_status);
 416                         udelay(5);
 417                         count--;
 418                 } while (((pll_status & ~0x3) != (u32)mfn) && count > 0);
 419
 420                 if (count <= 0) {
 421                         printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n", pll_status, mfn);
 422                         return -EIO;
 423                 }
 424         }
 425
 426         return 0;
 427 }
 428
 429 int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn)
 430 {
 431         struct ana_pll_dfs *dfs;
 432         u32 val;
 433         u32 index;
 434
 435         switch (pll_pfd) {
 436         case SYS_PLL_PFD0:
 437         case SYS_PLL_PFD0_DIV2:
 438                 index = 0;
 439                 break;
 440         case SYS_PLL_PFD1:
 441         case SYS_PLL_PFD1_DIV2:
 442                 index = 1;
 443                 break;
 444         case SYS_PLL_PFD2:
 445         case SYS_PLL_PFD2_DIV2:
 446                 index = 2;
 447                 break;
 448         default:
 449                 printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd);
 450                 return -EINVAL;
 451         }
 452
 453         dfs = &ana_regs->sys_pll.dfs[index];
 454
 455         val = readl(&dfs->dfs_div.reg);
 456         val &= ~0x3;
 457         val |= mfn & 0x3;
 458         writel(val, &dfs->dfs_div.reg);
 459
 460         return 0;
 461 }
 462
 463 /* return in khz */
 464 u32 get_clk_src_rate(enum ccm_clk_src source)
 465 {
 466         u32 ctrl;
 467         bool clk_on;
 468
 469         switch (source) {
 470         case ARM_PLL_CLK:
 471                 ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
 472         case AUDIO_PLL_CLK:
 473                 ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
 474                 break;
 475         case DRAM_PLL_CLK:
 476                 ctrl = readl(&ana_regs->dram_pll.ctrl.reg);
 477                 break;
 478         case VIDEO_PLL_CLK:
 479                 ctrl = readl(&ana_regs->video_pll.ctrl.reg);
 480                 break;
 481         case SYS_PLL_PFD0:
 482         case SYS_PLL_PFD0_DIV2:
 483                 ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg);
 484                 break;
 485         case SYS_PLL_PFD1:
 486         case SYS_PLL_PFD1_DIV2:
 487                 ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg);
 488                 break;
 489         case SYS_PLL_PFD2:
 490         case SYS_PLL_PFD2_DIV2:
 491                 ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg);
 492                 break;
 493         case OSC_24M_CLK:
 494                 return 24000;
 495         default:
 496                 printf("Invalid clock source to get rate\n");
 497                 return 0;
 498         }
 499
 500         if (ctrl & PLL_CTRL_HW_CTRL_SEL) {
 501                 /* When using HW ctrl, check OSCPLL */
 502                 clk_on = ccm_clk_src_is_clk_on(source);
 503                 if (clk_on)
 504                         return decode_pll(source);
 505                 else
 506                         return 0;
 507         } else {
 508                 /* controlled by pll registers */
 509                 return decode_pll(source);
 510         }
 511 }
 512
 513 u32 get_arm_core_clk(void)
 514 {
 515         u32 val;
 516
 517         ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val);
 518
 519         if (val & SHARED_GPR_A55_CLK_SEL_PLL)
 520                 return decode_pll(ARM_PLL_CLK) * 1000;
 521
 522         return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT);
 523 }
 524
 525 unsigned int mxc_get_clock(enum mxc_clock clk)
 526 {
 527         switch (clk) {
 528         case MXC_ARM_CLK:
 529                 return get_arm_core_clk();
 530         case MXC_IPG_CLK:
 531                 return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT);
 532         case MXC_CSPI_CLK:
 533                 return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT);
 534         case MXC_ESDHC_CLK:
 535                 return ccm_clk_root_get_rate(USDHC1_CLK_ROOT);
 536         case MXC_ESDHC2_CLK:
 537                 return ccm_clk_root_get_rate(USDHC2_CLK_ROOT);
 538         case MXC_ESDHC3_CLK:
 539                 return ccm_clk_root_get_rate(USDHC3_CLK_ROOT);
 540         case MXC_UART_CLK:
 541                 return ccm_clk_root_get_rate(LPUART1_CLK_ROOT);
 542         case MXC_FLEXSPI_CLK:
 543                 return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT);
 544         default:
 545                 return -1;
 546         };
 547
 548         return -1;
 549 };
 550
 551 int enable_i2c_clk(unsigned char enable, u32 i2c_num)
 552 {
 553         if (i2c_num > 7)
 554                 return -EINVAL;
 555
 556         if (enable) {
 557                 /* 24M */
 558                 ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
 559                 ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1);
 560                 ccm_lpcg_on(CCGR_I2C1 + i2c_num, true);
 561         } else {
 562                 ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
 563         }
 564
 565         return 0;
 566 }
 567
 568 u32 imx_get_i2cclk(u32 i2c_num)
 569 {
 570         if (i2c_num > 7)
 571                 return -EINVAL;
 572
 573         return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num);
 574 }
 575
 576 u32 get_lpuart_clk(void)
 577 {
 578         return mxc_get_clock(MXC_UART_CLK);
 579 }
 580
 581 void init_uart_clk(u32 index)
 582 {
 583         switch (index) {
 584         case LPUART1_CLK_ROOT:
 585                 /* 24M */
 586                 ccm_lpcg_on(CCGR_URT1, false);
 587                 ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1);
 588                 ccm_lpcg_on(CCGR_URT1, true);
 589                 break;
 590         default:
 591                 break;
 592         }
 593 }
 594
 595 void init_clk_usdhc(u32 index)
 596 {
 597         /* 400 Mhz */
 598         switch (index) {
 599         case 0:
 600                 ccm_lpcg_on(CCGR_USDHC1, 0);
 601                 ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
 602                 ccm_lpcg_on(CCGR_USDHC1, 1);
 603                 break;
 604         case 1:
 605                 ccm_lpcg_on(CCGR_USDHC2, 0);
 606                 ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
 607                 ccm_lpcg_on(CCGR_USDHC2, 1);
 608                 break;
 609         case 2:
 610                 ccm_lpcg_on(CCGR_USDHC3, 0);
 611                 ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
 612                 ccm_lpcg_on(CCGR_USDHC3, 1);
 613                 break;
 614         default:
 615                 return;
 616         };
 617 }
 618
 619 void enable_usboh3_clk(unsigned char enable)
 620 {
 621         if (enable) {
 622                 ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 623                 ccm_lpcg_on(CCGR_USBC, 1);
 624         } else {
 625                 ccm_lpcg_on(CCGR_USBC, 0);
 626         }
 627 }
 628
 629 #ifdef CONFIG_SPL_BUILD
 630 void dram_pll_init(ulong pll_val)
 631 {
 632         configure_fracpll(DRAM_PLL_CLK, pll_val);
 633 }
 634
 635 void dram_enable_bypass(ulong clk_val)
 636 {
 637         switch (clk_val) {
 638         case MHZ(400):
 639                 ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
 640                 break;
 641         case MHZ(333):
 642                 ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
 643                 break;
 644         case MHZ(200):
 645                 ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
 646                 break;
 647         case MHZ(100):
 648                 ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
 649                 break;
 650         default:
 651                 printf("No matched freq table %lu\n", clk_val);
 652                 return;
 653         }
 654
 655         /* Set DRAM APB to 133Mhz */
 656         ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 657         /* Switch from DRAM  clock root from PLL to CCM */
 658         ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
 659 }
 660
 661 void dram_disable_bypass(void)
 662 {
 663         /* Set DRAM APB to 133Mhz */
 664         ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 665         /* Switch from DRAM  clock root from CCM to PLL */
 666         ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
 667 }
 668
 669 void set_arm_clk(ulong freq)
 670 {
 671         /* Increase ARM clock to 1.7Ghz */
 672         ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
 673         configure_intpll(ARM_PLL_CLK, 1700000000);
 674         ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
 675 }
 676
 677 #endif
 678
 679 int clock_init(void)
 680 {
 681         int i;
 682
 683         /* Set A55 periphal to 333M */
 684         ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
 685         /* Set A55 mtr bus to 133M */
 686         ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 687
 688         /* Sentinel to 200M */
 689         ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
 690         /* Bus_wakeup to 133M */
 691         ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 692         /* Bus_AON to 133M */
 693         ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 694         /* M33 to 200M */
 695         ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
 696         /*
 697          * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
 698          * generating MII clock at 2.5M
 699          */
 700         ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
 701         /* SWO TRACE to 133M */
 702         ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 703         /* M33 systetick to 133M */
 704         ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 705         /* NIC to 400M */
 706         ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
 707         /* NIC_APB to 133M */
 708         ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 709
 710         /* allow for non-secure access */
 711         for (i = 0; i < OSCPLL_END; i++)
 712                 ccm_clk_src_tz_access(i, true, false, false);
 713
 714         for (i = 0; i < CLK_ROOT_NUM; i++)
 715                 ccm_clk_root_tz_access(i, true, false, false);
 716
 717         for (i = 0; i < CCGR_NUM; i++)
 718                 ccm_lpcg_tz_access(i, true, false, false);
 719
 720         for (i = 0; i < SHARED_GPR_NUM; i++)
 721                 ccm_shared_gpr_tz_access(i, true, false, false);
 722
 723         return 0;
 724 }
 725
 726 int set_clk_eqos(enum enet_freq type)
 727 {
 728         u32 eqos_post_div;
 729
 730         switch (type) {
 731         case ENET_125MHZ:
 732                 eqos_post_div = 2; /* 250M clock */
 733                 break;
 734         case ENET_50MHZ:
 735                 eqos_post_div = 5; /* 100M clock */
 736                 break;
 737         case ENET_25MHZ:
 738                 eqos_post_div = 10; /* 50M clock*/
 739                 break;
 740         default:
 741                 return -EINVAL;
 742         }
 743
 744         /* disable the clock first */
 745         ccm_lpcg_on(CCGR_ENETQOS, false);
 746
 747         ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div);
 748         ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
 749
 750         /* enable clock */
 751         ccm_lpcg_on(CCGR_ENETQOS, true);
 752
 753         return 0;
 754 }
 755
 756 u32 imx_get_eqos_csr_clk(void)
 757 {
 758         return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
 759 }
 760
 761 u32 imx_get_fecclk(void)
 762 {
 763         return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
 764 }
 765
 766 int set_clk_enet(enum enet_freq type)
 767 {
 768         u32 div;
 769
 770         /* disable the clock first */
 771         ccm_lpcg_on(CCGR_ENET1, false);
 772
 773         switch (type) {
 774         case ENET_125MHZ:
 775                 div = 2; /* 250Mhz */
 776                 break;
 777         case ENET_50MHZ:
 778                 div = 5; /* 100Mhz */
 779                 break;
 780         case ENET_25MHZ:
 781                 div = 10; /* 50Mhz */
 782                 break;
 783         default:
 784                 return -EINVAL;
 785         }
 786
 787         ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
 788         ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
 789
 790 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
 791         ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
 792 #endif
 793
 794         /* enable clock */
 795         ccm_lpcg_on(CCGR_ENET1, true);
 796
 797         return 0;
 798 }
 799
 800 /*
 801  * Dump some clockes.
 802  */
 803 #ifndef CONFIG_SPL_BUILD
 804 int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
 805 {
 806         u32 freq;
 807
 808         freq = decode_pll(ARM_PLL_CLK);
 809         printf("ARM_PLL    %8d MHz\n", freq / 1000);
 810         freq = decode_pll(DRAM_PLL_CLK);
 811         printf("DRAM_PLL    %8d MHz\n", freq / 1000);
 812         freq = decode_pll(SYS_PLL_PFD0);
 813         printf("SYS_PLL_PFD0    %8d MHz\n", freq / 1000);
 814         freq = decode_pll(SYS_PLL_PFD0_DIV2);
 815         printf("SYS_PLL_PFD0_DIV2    %8d MHz\n", freq / 1000);
 816         freq = decode_pll(SYS_PLL_PFD1);
 817         printf("SYS_PLL_PFD1    %8d MHz\n", freq / 1000);
 818         freq = decode_pll(SYS_PLL_PFD1_DIV2);
 819         printf("SYS_PLL_PFD1_DIV2    %8d MHz\n", freq / 1000);
 820         freq = decode_pll(SYS_PLL_PFD2);
 821         printf("SYS_PLL_PFD2    %8d MHz\n", freq / 1000);
 822         freq = decode_pll(SYS_PLL_PFD2_DIV2);
 823         printf("SYS_PLL_PFD2_DIV2    %8d MHz\n", freq / 1000);
 824         freq = mxc_get_clock(MXC_ARM_CLK);
 825         printf("ARM CORE    %8d MHz\n", freq / 1000000);
 826         freq = mxc_get_clock(MXC_IPG_CLK);
 827         printf("IPG         %8d MHz\n", freq / 1000000);
 828         freq = mxc_get_clock(MXC_UART_CLK);
 829         printf("UART3          %8d MHz\n", freq / 1000000);
 830         freq = mxc_get_clock(MXC_ESDHC_CLK);
 831         printf("USDHC1         %8d MHz\n", freq / 1000000);
 832         freq = mxc_get_clock(MXC_FLEXSPI_CLK);
 833         printf("FLEXSPI           %8d MHz\n", freq / 1000000);
 834
 835         return 0;
 836 }
 837
 838 U_BOOT_CMD(
 839         clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
 840         "display clocks",
 841         ""
 842 );
 843 #endif