arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019, 2021 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <event.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/mach-imx/hab.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/syscounter.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/armv8/mmu.h>
  23 #include <dm/uclass.h>
  24 #include <dm/device.h>
  25 #include <efi_loader.h>
  26 #include <env.h>
  27 #include <env_internal.h>
  28 #include <errno.h>
  29 #include <fdt_support.h>
  30 #include <fsl_wdog.h>
  31 #include <imx_sip.h>
  32 #include <linux/bitops.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #if defined(CONFIG_IMX_HAB)
  37 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  38         .bank = 1,
  39         .word = 3,
  40 };
  41 #endif
  42
  43 int timer_init(void)
  44 {
  45 #ifdef CONFIG_SPL_BUILD
  46         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  47         unsigned long freq = readl(&sctr->cntfid0);
  48
  49         /* Update with accurate clock frequency */
  50         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  51
  52         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  53                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  54 #endif
  55
  56         gd->arch.tbl = 0;
  57         gd->arch.tbu = 0;
  58
  59         return 0;
  60 }
  61
  62 void enable_tzc380(void)
  63 {
  64         struct iomuxc_gpr_base_regs *gpr =
  65                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  66
  67         /* Enable TZASC and lock setting */
  68         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  69         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  70
  71         /*
  72          * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
  73          * order to avoid AXI Bus errors when GPU is in use
  74          */
  75         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
  76
  77         /*
  78          * imx8mn and imx8mp implements the lock bit for
  79          * TZASC_ID_SWAP_BYPASS, enable it to lock settings
  80          */
  81         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
  82
  83         /*
  84          * set Region 0 attribute to allow secure and non-secure
  85          * read/write permission. Found some masters like usb dwc3
  86          * controllers can't work with secure memory.
  87          */
  88         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  89 }
  90
  91 void set_wdog_reset(struct wdog_regs *wdog)
  92 {
  93         /*
  94          * Output WDOG_B signal to reset external pmic or POR_B decided by
  95          * the board design. Without external reset, the peripherals/DDR/
  96          * PMIC are not reset, that may cause system working abnormal.
  97          * WDZST bit is write-once only bit. Align this bit in kernel,
  98          * otherwise kernel code will have no chance to set this bit.
  99          */
 100         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
 101 }
 102
 103 #ifdef CONFIG_ARMV8_PSCI
 104 #define PTE_MAP_NS      PTE_BLOCK_NS
 105 #else
 106 #define PTE_MAP_NS      0
 107 #endif
 108
 109 static struct mm_region imx8m_mem_map[] = {
 110         {
 111                 /* ROM */
 112                 .virt = 0x0UL,
 113                 .phys = 0x0UL,
 114                 .size = 0x100000UL,
 115                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 116                          PTE_BLOCK_OUTER_SHARE
 117         }, {
 118                 /* CAAM */
 119                 .virt = 0x100000UL,
 120                 .phys = 0x100000UL,
 121                 .size = 0x8000UL,
 122                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 123                          PTE_BLOCK_NON_SHARE |
 124                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 125         }, {
 126                 /* OCRAM_S */
 127                 .virt = 0x180000UL,
 128                 .phys = 0x180000UL,
 129                 .size = 0x8000UL,
 130                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 131                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 132         }, {
 133                 /* TCM */
 134                 .virt = 0x7C0000UL,
 135                 .phys = 0x7C0000UL,
 136                 .size = 0x80000UL,
 137                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 138                          PTE_BLOCK_NON_SHARE |
 139                          PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
 140         }, {
 141                 /* OCRAM */
 142                 .virt = 0x900000UL,
 143                 .phys = 0x900000UL,
 144                 .size = 0x200000UL,
 145                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 146                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 147         }, {
 148                 /* AIPS */
 149                 .virt = 0xB00000UL,
 150                 .phys = 0xB00000UL,
 151                 .size = 0x3f500000UL,
 152                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 153                          PTE_BLOCK_NON_SHARE |
 154                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 155         }, {
 156                 /* DRAM1 */
 157                 .virt = 0x40000000UL,
 158                 .phys = 0x40000000UL,
 159                 .size = PHYS_SDRAM_SIZE,
 160                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 161                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 162 #ifdef PHYS_SDRAM_2_SIZE
 163         }, {
 164                 /* DRAM2 */
 165                 .virt = 0x100000000UL,
 166                 .phys = 0x100000000UL,
 167                 .size = PHYS_SDRAM_2_SIZE,
 168                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 169                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 170 #endif
 171         }, {
 172                 /* empty entrie to split table entry 5 if needed when TEEs are used */
 173                 0,
 174         }, {
 175                 /* List terminator */
 176                 0,
 177         }
 178 };
 179
 180 struct mm_region *mem_map = imx8m_mem_map;
 181
 182 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
 183 {
 184         int i;
 185
 186         for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
 187                 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
 188                         return i;
 189
 190         hang(); /* Entry not found, this must never happen. */
 191 }
 192
 193 void enable_caches(void)
 194 {
 195         /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
 196          * If OPTEE does not run, still update the MMU table according to dram banks structure
 197          * to set correct dram size from board_phys_sdram_size
 198          */
 199         int i = 0;
 200         /*
 201          * please make sure that entry initial value matches
 202          * imx8m_mem_map for DRAM1
 203          */
 204         int entry = imx8m_find_dram_entry_in_mem_map();
 205         u64 attrs = imx8m_mem_map[entry].attrs;
 206
 207         while (i < CONFIG_NR_DRAM_BANKS &&
 208                entry < ARRAY_SIZE(imx8m_mem_map)) {
 209                 if (gd->bd->bi_dram[i].start == 0)
 210                         break;
 211                 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
 212                 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
 213                 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
 214                 imx8m_mem_map[entry].attrs = attrs;
 215                 debug("Added memory mapping (%d): %llx %llx\n", entry,
 216                       imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
 217                 i++; entry++;
 218         }
 219
 220         icache_enable();
 221         dcache_enable();
 222 }
 223
 224 __weak int board_phys_sdram_size(phys_size_t *size)
 225 {
 226         if (!size)
 227                 return -EINVAL;
 228
 229         *size = PHYS_SDRAM_SIZE;
 230
 231 #ifdef PHYS_SDRAM_2_SIZE
 232         *size += PHYS_SDRAM_2_SIZE;
 233 #endif
 234         return 0;
 235 }
 236
 237 int dram_init(void)
 238 {
 239         phys_size_t sdram_size;
 240         int ret;
 241
 242         ret = board_phys_sdram_size(&sdram_size);
 243         if (ret)
 244                 return ret;
 245
 246         /* rom_pointer[1] contains the size of TEE occupies */
 247         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
 248                 gd->ram_size = sdram_size - rom_pointer[1];
 249         else
 250                 gd->ram_size = sdram_size;
 251
 252         return 0;
 253 }
 254
 255 int dram_init_banksize(void)
 256 {
 257         int bank = 0;
 258         int ret;
 259         phys_size_t sdram_size;
 260         phys_size_t sdram_b1_size, sdram_b2_size;
 261
 262         ret = board_phys_sdram_size(&sdram_size);
 263         if (ret)
 264                 return ret;
 265
 266         /* Bank 1 can't cross over 4GB space */
 267         if (sdram_size > 0xc0000000) {
 268                 sdram_b1_size = 0xc0000000;
 269                 sdram_b2_size = sdram_size - 0xc0000000;
 270         } else {
 271                 sdram_b1_size = sdram_size;
 272                 sdram_b2_size = 0;
 273         }
 274
 275         gd->bd->bi_dram[bank].start = PHYS_SDRAM;
 276         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
 277                 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 278                 phys_size_t optee_size = (size_t)rom_pointer[1];
 279
 280                 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
 281                 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 282                         if (++bank >= CONFIG_NR_DRAM_BANKS) {
 283                                 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 284                                 return -1;
 285                         }
 286
 287                         gd->bd->bi_dram[bank].start = optee_start + optee_size;
 288                         gd->bd->bi_dram[bank].size = PHYS_SDRAM +
 289                                 sdram_b1_size - gd->bd->bi_dram[bank].start;
 290                 }
 291         } else {
 292                 gd->bd->bi_dram[bank].size = sdram_b1_size;
 293         }
 294
 295         if (sdram_b2_size) {
 296                 if (++bank >= CONFIG_NR_DRAM_BANKS) {
 297                         puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 298                         return -1;
 299                 }
 300                 gd->bd->bi_dram[bank].start = 0x100000000UL;
 301                 gd->bd->bi_dram[bank].size = sdram_b2_size;
 302         }
 303
 304         return 0;
 305 }
 306
 307 phys_size_t get_effective_memsize(void)
 308 {
 309         int ret;
 310         phys_size_t sdram_size;
 311         phys_size_t sdram_b1_size;
 312         ret = board_phys_sdram_size(&sdram_size);
 313         if (!ret) {
 314                 /* Bank 1 can't cross over 4GB space */
 315                 if (sdram_size > 0xc0000000) {
 316                         sdram_b1_size = 0xc0000000;
 317                 } else {
 318                         sdram_b1_size = sdram_size;
 319                 }
 320
 321                 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
 322                     rom_pointer[1]) {
 323                         /* We will relocate u-boot to Top of dram1. Tee position has two cases:
 324                          * 1. At the top of dram1,  Then return the size removed optee size.
 325                          * 2. In the middle of dram1, return the size of dram1.
 326                          */
 327                         if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
 328                                 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
 329                 }
 330
 331                 return sdram_b1_size;
 332         } else {
 333                 return PHYS_SDRAM_SIZE;
 334         }
 335 }
 336
 337 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 338 {
 339         ulong top_addr;
 340
 341         /*
 342          * Some IPs have their accessible address space restricted by
 343          * the interconnect. Let's make sure U-Boot only ever uses the
 344          * space below the 4G address boundary (which is 3GiB big),
 345          * even when the effective available memory is bigger.
 346          */
 347         top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
 348
 349         /*
 350          * rom_pointer[0] stores the TEE memory start address.
 351          * rom_pointer[1] stores the size TEE uses.
 352          * We need to reserve the memory region for TEE.
 353          */
 354         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
 355             rom_pointer[1] && top_addr > rom_pointer[0])
 356                 top_addr = rom_pointer[0];
 357
 358         return top_addr;
 359 }
 360
 361 static u32 get_cpu_variant_type(u32 type)
 362 {
 363         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 364         struct fuse_bank *bank = &ocotp->bank[1];
 365         struct fuse_bank1_regs *fuse =
 366                 (struct fuse_bank1_regs *)bank->fuse_regs;
 367
 368         u32 value = readl(&fuse->tester4);
 369
 370         if (type == MXC_CPU_IMX8MQ) {
 371                 if ((value & 0x3) == 0x2)
 372                         return MXC_CPU_IMX8MD;
 373                 else if (value & 0x200000)
 374                         return MXC_CPU_IMX8MQL;
 375
 376         } else if (type == MXC_CPU_IMX8MM) {
 377                 switch (value & 0x3) {
 378                 case 2:
 379                         if (value & 0x1c0000)
 380                                 return MXC_CPU_IMX8MMDL;
 381                         else
 382                                 return MXC_CPU_IMX8MMD;
 383                 case 3:
 384                         if (value & 0x1c0000)
 385                                 return MXC_CPU_IMX8MMSL;
 386                         else
 387                                 return MXC_CPU_IMX8MMS;
 388                 default:
 389                         if (value & 0x1c0000)
 390                                 return MXC_CPU_IMX8MML;
 391                         break;
 392                 }
 393         } else if (type == MXC_CPU_IMX8MN) {
 394                 switch (value & 0x3) {
 395                 case 2:
 396                         if (value & 0x1000000) {
 397                                 if (value & 0x10000000)  /* MIPI DSI */
 398                                         return MXC_CPU_IMX8MNUD;
 399                                 else
 400                                         return MXC_CPU_IMX8MNDL;
 401                         } else {
 402                                 return MXC_CPU_IMX8MND;
 403                         }
 404                 case 3:
 405                         if (value & 0x1000000) {
 406                                 if (value & 0x10000000)  /* MIPI DSI */
 407                                         return MXC_CPU_IMX8MNUS;
 408                                 else
 409                                         return MXC_CPU_IMX8MNSL;
 410                         } else {
 411                                 return MXC_CPU_IMX8MNS;
 412                         }
 413                 default:
 414                         if (value & 0x1000000) {
 415                                 if (value & 0x10000000)  /* MIPI DSI */
 416                                         return MXC_CPU_IMX8MNUQ;
 417                                 else
 418                                         return MXC_CPU_IMX8MNL;
 419                         }
 420                         break;
 421                 }
 422         } else if (type == MXC_CPU_IMX8MP) {
 423                 u32 value0 = readl(&fuse->tester3);
 424                 u32 flag = 0;
 425
 426                 if ((value0 & 0xc0000) == 0x80000)
 427                         return MXC_CPU_IMX8MPD;
 428
 429                         /* vpu disabled */
 430                 if ((value0 & 0x43000000) == 0x43000000)
 431                         flag = 1;
 432
 433                 /* npu disabled*/
 434                 if ((value & 0x8) == 0x8)
 435                         flag |= BIT(1);
 436
 437                 /* isp disabled */
 438                 if ((value & 0x3) == 0x3)
 439                         flag |= BIT(2);
 440
 441                 /* gpu disabled */
 442                 if ((value & 0xc0) == 0xc0)
 443                         flag |= BIT(3);
 444
 445                 /* lvds disabled */
 446                 if ((value & 0x180000) == 0x180000)
 447                         flag |= BIT(4);
 448
 449                 /* mipi dsi disabled */
 450                 if ((value & 0x60000) == 0x60000)
 451                         flag |= BIT(5);
 452
 453                 switch (flag) {
 454                 case 0x3f:
 455                         return MXC_CPU_IMX8MPUL;
 456                 case 7:
 457                         return MXC_CPU_IMX8MPL;
 458                 case 2:
 459                         return MXC_CPU_IMX8MP6;
 460                 default:
 461                         break;
 462                 }
 463
 464         }
 465
 466         return type;
 467 }
 468
 469 u32 get_cpu_rev(void)
 470 {
 471         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 472         u32 reg = readl(&ana_pll->digprog);
 473         u32 type = (reg >> 16) & 0xff;
 474         u32 major_low = (reg >> 8) & 0xff;
 475         u32 rom_version;
 476
 477         reg &= 0xff;
 478
 479         /* iMX8MP */
 480         if (major_low == 0x43) {
 481                 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
 482         } else if (major_low == 0x42) {
 483                 /* iMX8MN */
 484                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 485         } else if (major_low == 0x41) {
 486                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 487         } else {
 488                 if (reg == CHIP_REV_1_0) {
 489                         /*
 490                          * For B0 chip, the DIGPROG is not updated,
 491                          * it is still TO1.0. we have to check ROM
 492                          * version or OCOTP_READ_FUSE_DATA.
 493                          * 0xff0055aa is magic number for B1.
 494                          */
 495                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 496                                 /*
 497                                  * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
 498                                  * so have to check ROM to distinguish them
 499                                  */
 500                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
 501                                 rom_version &= 0xff;
 502                                 if (rom_version == CHIP_REV_2_2)
 503                                         reg = CHIP_REV_2_2;
 504                                 else
 505                                         reg = CHIP_REV_2_1;
 506                         } else {
 507                                 rom_version =
 508                                         readl((void __iomem *)ROM_VERSION_A0);
 509                                 if (rom_version != CHIP_REV_1_0) {
 510                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 511                                         rom_version &= 0xff;
 512                                         if (rom_version == CHIP_REV_2_0)
 513                                                 reg = CHIP_REV_2_0;
 514                                 }
 515                         }
 516                 }
 517
 518                 type = get_cpu_variant_type(type);
 519         }
 520
 521         return (type << 12) | reg;
 522 }
 523
 524 static void imx_set_wdog_powerdown(bool enable)
 525 {
 526         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 527         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 528         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 529
 530         /* Write to the PDE (Power Down Enable) bit */
 531         writew(enable, &wdog1->wmcr);
 532         writew(enable, &wdog2->wmcr);
 533         writew(enable, &wdog3->wmcr);
 534 }
 535
 536 static int imx8m_check_clock(void *ctx, struct event *event)
 537 {
 538         struct udevice *dev;
 539         int ret;
 540
 541         if (CONFIG_IS_ENABLED(CLK)) {
 542                 ret = uclass_get_device_by_name(UCLASS_CLK,
 543                                                 "clock-controller@30380000",
 544                                                 &dev);
 545                 if (ret < 0) {
 546                         printf("Failed to find clock node. Check device tree\n");
 547                         return ret;
 548                 }
 549         }
 550
 551         return 0;
 552 }
 553 EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
 554
 555 static void imx8m_setup_snvs(void)
 556 {
 557         /* Enable SNVS clock */
 558         clock_enable(CCGR_SNVS, 1);
 559         /* Initialize glitch detect */
 560         writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
 561         /* Clear interrupt status */
 562         writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
 563 }
 564
 565 static void imx8m_setup_csu_tzasc(void)
 566 {
 567         const uintptr_t tzasc_base[4] = {
 568                 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
 569         };
 570         int i, j;
 571
 572         if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
 573                 return;
 574
 575         /* CSU */
 576         for (i = 0; i < 64; i++)
 577                 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
 578
 579         /* TZASC */
 580         for (j = 0; j < 4; j++) {
 581                 writel(0x77777777, (void *)(tzasc_base[j]));
 582                 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
 583                 for (i = 0; i <= 0x10; i += 4)
 584                         writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
 585         }
 586 }
 587
 588 int arch_cpu_init(void)
 589 {
 590         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 591
 592 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 593         icache_enable();
 594 #endif
 595
 596         /*
 597          * ROM might disable clock for SCTR,
 598          * enable the clock before timer_init.
 599          */
 600         if (IS_ENABLED(CONFIG_SPL_BUILD))
 601                 clock_enable(CCGR_SCTR, 1);
 602         /*
 603          * Init timer at very early state, because sscg pll setting
 604          * will use it
 605          */
 606         timer_init();
 607
 608         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 609                 clock_init();
 610                 imx_set_wdog_powerdown(false);
 611
 612                 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
 613                     is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
 614                     is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
 615                         /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
 616                         struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
 617                         struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
 618                         struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
 619                         struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
 620
 621                         writel(0x1, &pgc_core2->pgcr);
 622                         writel(0x1, &pgc_core3->pgcr);
 623                         if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
 624                                 writel(0x1, &pgc_core1->pgcr);
 625                                 writel(0xE, &gpc->cpu_pgc_dn_trg);
 626                         } else {
 627                                 writel(0xC, &gpc->cpu_pgc_dn_trg);
 628                         }
 629                 }
 630         }
 631
 632         if (is_imx8mq()) {
 633                 clock_enable(CCGR_OCOTP, 1);
 634                 if (readl(&ocotp->ctrl) & 0x200)
 635                         writel(0x200, &ocotp->ctrl_clr);
 636         }
 637
 638         imx8m_setup_snvs();
 639
 640         imx8m_setup_csu_tzasc();
 641
 642         return 0;
 643 }
 644
 645 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 646 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 647 #endif
 648
 649 #if defined(CONFIG_IMX8M)
 650 #include <spl.h>
 651 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 652 {
 653         u32 *rom_log_addr = (u32 *)0x9e0;
 654         u32 *rom_log;
 655         u8 event_id;
 656         int i, part;
 657
 658         part = default_spl_mmc_emmc_boot_partition(mmc);
 659
 660         /* If the ROM event log pointer is not valid. */
 661         if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
 662             *rom_log_addr & 0x3)
 663                 return part;
 664
 665         /* Parse the ROM event ID version 2 log */
 666         rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
 667         for (i = 0; i < 128; i++) {
 668                 event_id = rom_log[i] >> 24;
 669                 switch (event_id) {
 670                 case 0x00: /* End of list */
 671                         return part;
 672                 /* Log entries with 1 parameter, skip 1 */
 673                 case 0x80: /* Start to perform the device initialization */
 674                 case 0x81: /* The boot device initialization completes */
 675                 case 0x82: /* Starts to execute boot device driver pre-config */
 676                 case 0x8f: /* The boot device initialization fails */
 677                 case 0x90: /* Start to read data from boot device */
 678                 case 0x91: /* Reading data from boot device completes */
 679                 case 0x9f: /* Reading data from boot device fails */
 680                         i += 1;
 681                         continue;
 682                 /* Log entries with 2 parameters, skip 2 */
 683                 case 0xa0: /* Image authentication result */
 684                 case 0xc0: /* Jump to the boot image soon */
 685                         i += 2;
 686                         continue;
 687                 /* Boot from the secondary boot image */
 688                 case 0x51:
 689                         /*
 690                          * Swap the eMMC boot partitions in case there was a
 691                          * fallback event (i.e. primary image was corrupted
 692                          * and that corruption was recognized by the BootROM),
 693                          * so the SPL loads the rest of the U-Boot from the
 694                          * correct eMMC boot partition, since the BootROM
 695                          * leaves the boot partition set to the corrupted one.
 696                          */
 697                         if (part == 1)
 698                                 part = 2;
 699                         else if (part == 2)
 700                                 part = 1;
 701                         continue;
 702                 default:
 703                         continue;
 704                 }
 705         }
 706
 707         return part;
 708 }
 709 #endif
 710
 711 bool is_usb_boot(void)
 712 {
 713         return get_boot_device() == USB_BOOT;
 714 }
 715
 716 #ifdef CONFIG_OF_SYSTEM_SETUP
 717 bool check_fdt_new_path(void *blob)
 718 {
 719         const char *soc_path = "/soc@0";
 720         int nodeoff;
 721
 722         nodeoff = fdt_path_offset(blob, soc_path);
 723         if (nodeoff < 0)
 724                 return false;
 725
 726         return true;
 727 }
 728
 729 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
 730 {
 731         int i = 0;
 732         int rc;
 733         int nodeoff;
 734         const char *status = "disabled";
 735
 736         for (i = 0; i < size_array; i++) {
 737                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
 738                 if (nodeoff < 0)
 739                         continue; /* Not found, skip it */
 740
 741                 debug("Found %s node\n", nodes_path[i]);
 742
 743 add_status:
 744                 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
 745                 if (rc) {
 746                         if (rc == -FDT_ERR_NOSPACE) {
 747                                 rc = fdt_increase_size(blob, 512);
 748                                 if (!rc)
 749                                         goto add_status;
 750                         }
 751                         printf("Unable to update property %s:%s, err=%s\n",
 752                                nodes_path[i], "status", fdt_strerror(rc));
 753                 } else {
 754                         printf("Modify %s:%s disabled\n",
 755                                nodes_path[i], "status");
 756                 }
 757         }
 758
 759         return 0;
 760 }
 761
 762 #ifdef CONFIG_IMX8MQ
 763 bool check_dcss_fused(void)
 764 {
 765         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 766         struct fuse_bank *bank = &ocotp->bank[1];
 767         struct fuse_bank1_regs *fuse =
 768                 (struct fuse_bank1_regs *)bank->fuse_regs;
 769         u32 value = readl(&fuse->tester4);
 770
 771         if (value & 0x4000000)
 772                 return true;
 773
 774         return false;
 775 }
 776
 777 static int disable_mipi_dsi_nodes(void *blob)
 778 {
 779         static const char * const nodes_path[] = {
 780                 "/mipi_dsi@30A00000",
 781                 "/mipi_dsi_bridge@30A00000",
 782                 "/dsi_phy@30A00300",
 783                 "/soc@0/bus@30800000/mipi_dsi@30a00000",
 784                 "/soc@0/bus@30800000/dphy@30a00300",
 785                 "/soc@0/bus@30800000/mipi-dsi@30a00000",
 786         };
 787
 788         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 789 }
 790
 791 static int disable_dcss_nodes(void *blob)
 792 {
 793         static const char * const nodes_path[] = {
 794                 "/dcss@0x32e00000",
 795                 "/dcss@32e00000",
 796                 "/hdmi@32c00000",
 797                 "/hdmi_cec@32c33800",
 798                 "/hdmi_drm@32c00000",
 799                 "/display-subsystem",
 800                 "/sound-hdmi",
 801                 "/sound-hdmi-arc",
 802                 "/soc@0/bus@32c00000/display-controller@32e00000",
 803                 "/soc@0/bus@32c00000/hdmi@32c00000",
 804         };
 805
 806         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 807 }
 808
 809 static int check_mipi_dsi_nodes(void *blob)
 810 {
 811         static const char * const lcdif_path[] = {
 812                 "/lcdif@30320000",
 813                 "/soc@0/bus@30000000/lcdif@30320000",
 814                 "/soc@0/bus@30000000/lcd-controller@30320000"
 815         };
 816         static const char * const mipi_dsi_path[] = {
 817                 "/mipi_dsi@30A00000",
 818                 "/soc@0/bus@30800000/mipi_dsi@30a00000"
 819         };
 820         static const char * const lcdif_ep_path[] = {
 821                 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
 822                 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
 823                 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
 824         };
 825         static const char * const mipi_dsi_ep_path[] = {
 826                 "/mipi_dsi@30A00000/port@1/endpoint",
 827                 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
 828                 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
 829         };
 830
 831         int lookup_node;
 832         int nodeoff;
 833         bool new_path = check_fdt_new_path(blob);
 834         int i = new_path ? 1 : 0;
 835
 836         nodeoff = fdt_path_offset(blob, lcdif_path[i]);
 837         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
 838                 /*
 839                  * If can't find lcdif node or lcdif node is disabled,
 840                  * then disable all mipi dsi, since they only can input
 841                  * from DCSS
 842                  */
 843                 return disable_mipi_dsi_nodes(blob);
 844         }
 845
 846         nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
 847         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
 848                 return 0;
 849
 850         nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
 851         if (nodeoff < 0) {
 852                 /*
 853                  * If can't find lcdif endpoint, then disable all mipi dsi,
 854                  * since they only can input from DCSS
 855                  */
 856                 return disable_mipi_dsi_nodes(blob);
 857         }
 858
 859         lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
 860         nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
 861
 862         if (nodeoff > 0 && nodeoff == lookup_node)
 863                 return 0;
 864
 865         return disable_mipi_dsi_nodes(blob);
 866 }
 867 #endif
 868
 869 int disable_vpu_nodes(void *blob)
 870 {
 871         static const char * const nodes_path_8mq[] = {
 872                 "/vpu@38300000",
 873                 "/soc@0/vpu@38300000"
 874         };
 875
 876         static const char * const nodes_path_8mm[] = {
 877                 "/vpu_g1@38300000",
 878                 "/vpu_g2@38310000",
 879                 "/vpu_h1@38320000"
 880         };
 881
 882         static const char * const nodes_path_8mp[] = {
 883                 "/vpu_g1@38300000",
 884                 "/vpu_g2@38310000",
 885                 "/vpu_vc8000e@38320000"
 886         };
 887
 888         if (is_imx8mq())
 889                 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
 890         else if (is_imx8mm())
 891                 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
 892         else if (is_imx8mp())
 893                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 894         else
 895                 return -EPERM;
 896 }
 897
 898 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
 899 static int low_drive_gpu_freq(void *blob)
 900 {
 901         static const char *nodes_path_8mn[] = {
 902                 "/gpu@38000000",
 903                 "/soc@0/gpu@38000000"
 904         };
 905
 906         int nodeoff, cnt, i;
 907         u32 assignedclks[7];
 908
 909         nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
 910         if (nodeoff < 0)
 911                 return nodeoff;
 912
 913         cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
 914         if (cnt < 0)
 915                 return cnt;
 916
 917         if (cnt != 7)
 918                 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
 919         if (cnt < 2)
 920                 return -1;
 921
 922         assignedclks[cnt - 1] = 200000000;
 923         assignedclks[cnt - 2] = 200000000;
 924
 925         for (i = 0; i < cnt; i++) {
 926                 debug("<%u>, ", assignedclks[i]);
 927                 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
 928         }
 929         debug("\n");
 930
 931         return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
 932 }
 933 #endif
 934
 935 static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
 936 {
 937         int lookup_node;
 938         int nodeoff;
 939
 940         nodeoff = fdt_path_offset(blob, ep1);
 941         if (nodeoff) {
 942                 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
 943                 nodeoff = fdt_path_offset(blob, ep2);
 944
 945                 if (nodeoff > 0 && nodeoff == lookup_node)
 946                         return true;
 947         }
 948
 949         return false;
 950 }
 951
 952 int disable_dsi_lcdif_nodes(void *blob)
 953 {
 954         int ret;
 955
 956         static const char * const dsi_path_8mp[] = {
 957                 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
 958         };
 959
 960         static const char * const lcdif_path_8mp[] = {
 961                 "/soc@0/bus@32c00000/lcd-controller@32e80000"
 962         };
 963
 964         static const char * const lcdif_ep_path_8mp[] = {
 965                 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
 966         };
 967         static const char * const dsi_ep_path_8mp[] = {
 968                 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
 969         };
 970
 971         ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
 972         if (ret)
 973                 return ret;
 974
 975         if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
 976                 /* Disable lcdif node */
 977                 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
 978         }
 979
 980         return 0;
 981 }
 982
 983 int disable_lvds_lcdif_nodes(void *blob)
 984 {
 985         int ret, i;
 986
 987         static const char * const ldb_path_8mp[] = {
 988                 "/soc@0/bus@32c00000/ldb@32ec005c",
 989                 "/soc@0/bus@32c00000/phy@32ec0128"
 990         };
 991
 992         static const char * const lcdif_path_8mp[] = {
 993                 "/soc@0/bus@32c00000/lcd-controller@32e90000"
 994         };
 995
 996         static const char * const lcdif_ep_path_8mp[] = {
 997                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
 998                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
 999         };
1000         static const char * const ldb_ep_path_8mp[] = {
1001                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1002                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1003         };
1004
1005         ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1006         if (ret)
1007                 return ret;
1008
1009         for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1010                 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1011                         /* Disable lcdif node */
1012                         return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1013                 }
1014         }
1015
1016         return 0;
1017 }
1018
1019 int disable_gpu_nodes(void *blob)
1020 {
1021         static const char * const nodes_path_8mn[] = {
1022                 "/gpu@38000000",
1023                 "/soc@/gpu@38000000"
1024         };
1025
1026         static const char * const nodes_path_8mp[] = {
1027                 "/gpu3d@38000000",
1028                 "/gpu2d@38008000"
1029         };
1030
1031         if (is_imx8mp())
1032                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1033         else
1034                 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
1035 }
1036
1037 int disable_npu_nodes(void *blob)
1038 {
1039         static const char * const nodes_path_8mp[] = {
1040                 "/vipsi@38500000"
1041         };
1042
1043         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1044 }
1045
1046 int disable_isp_nodes(void *blob)
1047 {
1048         static const char * const nodes_path_8mp[] = {
1049                 "/soc@0/bus@32c00000/camera/isp@32e10000",
1050                 "/soc@0/bus@32c00000/camera/isp@32e20000"
1051         };
1052
1053         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1054 }
1055
1056 int disable_dsp_nodes(void *blob)
1057 {
1058         static const char * const nodes_path_8mp[] = {
1059                 "/dsp@3b6e8000"
1060         };
1061
1062         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1063 }
1064
1065 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1066 {
1067         static const char * const thermal_path[] = {
1068                 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1069         };
1070
1071         int nodeoff, cnt, i, ret, j;
1072         u32 cooling_dev[12];
1073
1074         for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1075                 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1076                 if (nodeoff < 0)
1077                         continue; /* Not found, skip it */
1078
1079                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1080                 if (cnt < 0)
1081                         continue;
1082
1083                 if (cnt != 12)
1084                         printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1085
1086                 for (j = 0; j < cnt; j++)
1087                         cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1088
1089                 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1090                                   sizeof(u32) * (12 - disabled_cores * 3));
1091                 if (ret < 0) {
1092                         printf("Warning: %s, cooling-device setprop failed %d\n",
1093                                thermal_path[i], ret);
1094                         continue;
1095                 }
1096
1097                 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1098         }
1099 }
1100
1101 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1102 {
1103         static const char * const pmu_path[] = {
1104                 "/pmu"
1105         };
1106
1107         int nodeoff, cnt, i, ret, j;
1108         u32 irq_affinity[4];
1109
1110         for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1111                 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1112                 if (nodeoff < 0)
1113                         continue; /* Not found, skip it */
1114
1115                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1116                                                  irq_affinity, 4);
1117                 if (cnt < 0)
1118                         continue;
1119
1120                 if (cnt != 4)
1121                         printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1122
1123                 for (j = 0; j < cnt; j++)
1124                         irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1125
1126                 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1127                                  sizeof(u32) * (4 - disabled_cores));
1128                 if (ret < 0) {
1129                         printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1130                                pmu_path[i], ret);
1131                         continue;
1132                 }
1133
1134                 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1135         }
1136 }
1137
1138 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1139 {
1140         static const char * const nodes_path[] = {
1141                 "/cpus/cpu@1",
1142                 "/cpus/cpu@2",
1143                 "/cpus/cpu@3",
1144         };
1145         u32 i = 0;
1146         int rc;
1147         int nodeoff;
1148
1149         if (disabled_cores > 3)
1150                 return -EINVAL;
1151
1152         i = 3 - disabled_cores;
1153
1154         for (; i < 3; i++) {
1155                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1156                 if (nodeoff < 0)
1157                         continue; /* Not found, skip it */
1158
1159                 debug("Found %s node\n", nodes_path[i]);
1160
1161                 rc = fdt_del_node(blob, nodeoff);
1162                 if (rc < 0) {
1163                         printf("Unable to delete node %s, err=%s\n",
1164                                nodes_path[i], fdt_strerror(rc));
1165                 } else {
1166                         printf("Delete node %s\n", nodes_path[i]);
1167                 }
1168         }
1169
1170         disable_thermal_cpu_nodes(blob, disabled_cores);
1171         disable_pmu_cpu_nodes(blob, disabled_cores);
1172
1173         return 0;
1174 }
1175
1176 static int cleanup_nodes_for_efi(void *blob)
1177 {
1178         static const char * const path[][2] = {
1179                 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1180                 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1181                 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1182                 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1183         };
1184         int nodeoff, i, rc;
1185
1186         for (i = 0; i < ARRAY_SIZE(path); i++) {
1187                 nodeoff = fdt_path_offset(blob, path[i][0]);
1188                 if (nodeoff < 0)
1189                         continue; /* Not found, skip it */
1190                 debug("Found %s node\n", path[i][0]);
1191
1192                 rc = fdt_delprop(blob, nodeoff, path[i][1]);
1193                 if (rc == -FDT_ERR_NOTFOUND)
1194                         continue;
1195                 if (rc) {
1196                         printf("Unable to update property %s:%s, err=%s\n",
1197                                path[i][0], path[i][1], fdt_strerror(rc));
1198                         return rc;
1199                 }
1200
1201                 printf("Remove %s:%s\n", path[i][0], path[i][1]);
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int fixup_thermal_trips(void *blob, const char *name)
1208 {
1209         int minc, maxc;
1210         int node, trip;
1211
1212         node = fdt_path_offset(blob, "/thermal-zones");
1213         if (node < 0)
1214                 return node;
1215
1216         node = fdt_subnode_offset(blob, node, name);
1217         if (node < 0)
1218                 return node;
1219
1220         node = fdt_subnode_offset(blob, node, "trips");
1221         if (node < 0)
1222                 return node;
1223
1224         get_cpu_temp_grade(&minc, &maxc);
1225
1226         fdt_for_each_subnode(trip, blob, node) {
1227                 const char *type;
1228                 int temp, ret;
1229
1230                 type = fdt_getprop(blob, trip, "type", NULL);
1231                 if (!type)
1232                         continue;
1233
1234                 temp = 0;
1235                 if (!strcmp(type, "critical"))
1236                         temp = 1000 * maxc;
1237                 else if (!strcmp(type, "passive"))
1238                         temp = 1000 * (maxc - 10);
1239                 if (temp) {
1240                         ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1241                         if (ret)
1242                                 return ret;
1243                 }
1244         }
1245
1246         return 0;
1247 }
1248
1249 int ft_system_setup(void *blob, struct bd_info *bd)
1250 {
1251 #ifdef CONFIG_IMX8MQ
1252         int i = 0;
1253         int rc;
1254         int nodeoff;
1255
1256         if (get_boot_device() == USB_BOOT) {
1257                 disable_dcss_nodes(blob);
1258
1259                 bool new_path = check_fdt_new_path(blob);
1260                 int v = new_path ? 1 : 0;
1261                 static const char * const usb_dwc3_path[] = {
1262                         "/usb@38100000/dwc3",
1263                         "/soc@0/usb@38100000"
1264                 };
1265
1266                 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1267                 if (nodeoff >= 0) {
1268                         const char *speed = "high-speed";
1269
1270                         debug("Found %s node\n", usb_dwc3_path[v]);
1271
1272 usb_modify_speed:
1273
1274                         rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1275                         if (rc) {
1276                                 if (rc == -FDT_ERR_NOSPACE) {
1277                                         rc = fdt_increase_size(blob, 512);
1278                                         if (!rc)
1279                                                 goto usb_modify_speed;
1280                                 }
1281                                 printf("Unable to set property %s:%s, err=%s\n",
1282                                        usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1283                         } else {
1284                                 printf("Modify %s:%s = %s\n",
1285                                        usb_dwc3_path[v], "maximum-speed", speed);
1286                         }
1287                 } else {
1288                         printf("Can't found %s node\n", usb_dwc3_path[v]);
1289                 }
1290         }
1291
1292         /* Disable the CPU idle for A0 chip since the HW does not support it */
1293         if (is_soc_rev(CHIP_REV_1_0)) {
1294                 static const char * const nodes_path[] = {
1295                         "/cpus/cpu@0",
1296                         "/cpus/cpu@1",
1297                         "/cpus/cpu@2",
1298                         "/cpus/cpu@3",
1299                 };
1300
1301                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1302                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
1303                         if (nodeoff < 0)
1304                                 continue; /* Not found, skip it */
1305
1306                         debug("Found %s node\n", nodes_path[i]);
1307
1308                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1309                         if (rc == -FDT_ERR_NOTFOUND)
1310                                 continue;
1311                         if (rc) {
1312                                 printf("Unable to update property %s:%s, err=%s\n",
1313                                        nodes_path[i], "status", fdt_strerror(rc));
1314                                 return rc;
1315                         }
1316
1317                         debug("Remove %s:%s\n", nodes_path[i],
1318                                "cpu-idle-states");
1319                 }
1320         }
1321
1322         if (is_imx8mql()) {
1323                 disable_vpu_nodes(blob);
1324                 if (check_dcss_fused()) {
1325                         printf("DCSS is fused\n");
1326                         disable_dcss_nodes(blob);
1327                         check_mipi_dsi_nodes(blob);
1328                 }
1329         }
1330
1331         if (is_imx8md())
1332                 disable_cpu_nodes(blob, 2);
1333
1334 #elif defined(CONFIG_IMX8MM)
1335         if (is_imx8mml() || is_imx8mmdl() ||  is_imx8mmsl())
1336                 disable_vpu_nodes(blob);
1337
1338         if (is_imx8mmd() || is_imx8mmdl())
1339                 disable_cpu_nodes(blob, 2);
1340         else if (is_imx8mms() || is_imx8mmsl())
1341                 disable_cpu_nodes(blob, 3);
1342
1343 #elif defined(CONFIG_IMX8MN)
1344         if (is_imx8mnl() || is_imx8mndl() ||  is_imx8mnsl())
1345                 disable_gpu_nodes(blob);
1346 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1347         else {
1348                 int ldm_gpu = low_drive_gpu_freq(blob);
1349
1350                 if (ldm_gpu < 0)
1351                         printf("Update GPU node assigned-clock-rates failed\n");
1352                 else
1353                         printf("Update GPU node assigned-clock-rates ok\n");
1354         }
1355 #endif
1356
1357         if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1358                 disable_cpu_nodes(blob, 2);
1359         else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1360                 disable_cpu_nodes(blob, 3);
1361
1362 #elif defined(CONFIG_IMX8MP)
1363         if (is_imx8mpul()) {
1364                 /* Disable GPU */
1365                 disable_gpu_nodes(blob);
1366
1367                 /* Disable DSI */
1368                 disable_dsi_lcdif_nodes(blob);
1369
1370                 /* Disable LVDS */
1371                 disable_lvds_lcdif_nodes(blob);
1372         }
1373
1374         if (is_imx8mpul() || is_imx8mpl())
1375                 disable_vpu_nodes(blob);
1376
1377         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1378                 disable_npu_nodes(blob);
1379
1380         if (is_imx8mpul() || is_imx8mpl())
1381                 disable_isp_nodes(blob);
1382
1383         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1384                 disable_dsp_nodes(blob);
1385
1386         if (is_imx8mpd())
1387                 disable_cpu_nodes(blob, 2);
1388 #endif
1389
1390         cleanup_nodes_for_efi(blob);
1391
1392         if (fixup_thermal_trips(blob, "cpu-thermal"))
1393                 printf("Failed to update cpu-thermal trip(s)");
1394         if (IS_ENABLED(CONFIG_IMX8MP) &&
1395             fixup_thermal_trips(blob, "soc-thermal"))
1396                 printf("Failed to update soc-thermal trip(s)");
1397
1398         return 0;
1399 }
1400 #endif
1401
1402 #if !CONFIG_IS_ENABLED(SYSRESET)
1403 void reset_cpu(void)
1404 {
1405         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1406
1407         /* Clear WDA to trigger WDOG_B immediately */
1408         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1409
1410         while (1) {
1411                 /*
1412                  * spin for .5 seconds before reset
1413                  */
1414         }
1415 }
1416 #endif
1417
1418 #if defined(CONFIG_ARCH_MISC_INIT)
1419 int arch_misc_init(void)
1420 {
1421         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1422                 struct udevice *dev;
1423                 int ret;
1424
1425                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1426                 if (ret)
1427                         printf("Failed to initialize caam_jr: %d\n", ret);
1428         }
1429
1430         return 0;
1431 }
1432 #endif
1433
1434 #if defined(CONFIG_SPL_BUILD)
1435 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1436 bool serror_need_skip = true;
1437
1438 void do_error(struct pt_regs *pt_regs)
1439 {
1440         /*
1441          * If stack is still in ROM reserved OCRAM not switch to SPL,
1442          * it is the ROM SError
1443          */
1444         ulong sp;
1445
1446         asm volatile("mov %0, sp" : "=r"(sp) : );
1447
1448         if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1449                 /* Check for ERR050342, imx8mq HDCP enabled parts */
1450                 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1451                         serror_need_skip = false;
1452                         return; /* Do nothing skip the SError in ROM */
1453                 }
1454
1455                 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1456                 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1457                         serror_need_skip = false;
1458                         return; /* Do nothing skip the SError in ROM */
1459                 }
1460         }
1461
1462         efi_restore_gd();
1463         printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
1464         show_regs(pt_regs);
1465         panic("Resetting CPU ...\n");
1466 }
1467 #endif
1468 #endif
1469
1470 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1471 enum env_location arch_env_get_location(enum env_operation op, int prio)
1472 {
1473         enum boot_device dev = get_boot_device();
1474
1475         if (prio)
1476                 return ENVL_UNKNOWN;
1477
1478         switch (dev) {
1479         case USB_BOOT:
1480                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1481                         return ENVL_SPI_FLASH;
1482                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1483                         return ENVL_NAND;
1484                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1485                         return ENVL_MMC;
1486                 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1487                         return ENVL_NOWHERE;
1488                 return ENVL_UNKNOWN;
1489         case QSPI_BOOT:
1490         case SPI_NOR_BOOT:
1491                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1492                         return ENVL_SPI_FLASH;
1493                 return ENVL_NOWHERE;
1494         case NAND_BOOT:
1495                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1496                         return ENVL_NAND;
1497                 return ENVL_NOWHERE;
1498         case SD1_BOOT:
1499         case SD2_BOOT:
1500         case SD3_BOOT:
1501         case MMC1_BOOT:
1502         case MMC2_BOOT:
1503         case MMC3_BOOT:
1504                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1505                         return ENVL_MMC;
1506                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1507                         return ENVL_EXT4;
1508                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1509                         return ENVL_FAT;
1510                 return ENVL_NOWHERE;
1511         default:
1512                 return ENVL_NOWHERE;
1513         }
1514 }
1515
1516 #endif
1517
1518 #ifdef CONFIG_IMX_BOOTAUX
1519 const struct rproc_att hostmap[] = {
1520         /* aux core , host core,  size */
1521         { 0x00000000, 0x007e0000, 0x00020000 },
1522         /* OCRAM_S */
1523         { 0x00180000, 0x00180000, 0x00008000 },
1524         /* OCRAM */
1525         { 0x00900000, 0x00900000, 0x00020000 },
1526         /* OCRAM */
1527         { 0x00920000, 0x00920000, 0x00020000 },
1528         /* QSPI Code - alias */
1529         { 0x08000000, 0x08000000, 0x08000000 },
1530         /* DDR (Code) - alias */
1531         { 0x10000000, 0x80000000, 0x0FFE0000 },
1532         /* TCML */
1533         { 0x1FFE0000, 0x007E0000, 0x00040000 },
1534         /* OCRAM_S */
1535         { 0x20180000, 0x00180000, 0x00008000 },
1536         /* OCRAM */
1537         { 0x20200000, 0x00900000, 0x00040000 },
1538         /* DDR (Data) */
1539         { 0x40000000, 0x40000000, 0x80000000 },
1540         { /* sentinel */ }
1541 };
1542
1543 const struct rproc_att *imx_bootaux_get_hostmap(void)
1544 {
1545         return hostmap;
1546 }
1547 #endif