1 // SPDX-License-Identifier: GPL-2.0+
5 * Peng Fan <peng.fan@nxp.com>
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/mach-imx/syscounter.h>
16 #include <asm/armv8/mmu.h>
17 #include <dm/uclass.h>
19 #include <fdt_support.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_IMX_HAB)
26 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
34 #ifdef CONFIG_SPL_BUILD
35 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
36 unsigned long freq = readl(&sctr->cntfid0);
38 /* Update with accurate clock frequency */
39 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
41 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
42 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
51 void enable_tzc380(void)
53 struct iomuxc_gpr_base_regs *gpr =
54 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
56 /* Enable TZASC and lock setting */
57 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
58 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
59 if (is_imx8mm() || is_imx8mn())
60 setbits_le32(&gpr->gpr[10], BIT(1));
62 * set Region 0 attribute to allow secure and non-secure
63 * read/write permission. Found some masters like usb dwc3
64 * controllers can't work with secure memory.
66 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
69 void set_wdog_reset(struct wdog_regs *wdog)
72 * Output WDOG_B signal to reset external pmic or POR_B decided by
73 * the board design. Without external reset, the peripherals/DDR/
74 * PMIC are not reset, that may cause system working abnormal.
75 * WDZST bit is write-once only bit. Align this bit in kernel,
76 * otherwise kernel code will have no chance to set this bit.
78 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
81 static struct mm_region imx8m_mem_map[] = {
87 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
94 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 PTE_BLOCK_PXN | PTE_BLOCK_UXN
102 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
103 PTE_BLOCK_NON_SHARE |
104 PTE_BLOCK_PXN | PTE_BLOCK_UXN
110 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
111 PTE_BLOCK_OUTER_SHARE
116 .size = 0x3f500000UL,
117 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
118 PTE_BLOCK_NON_SHARE |
119 PTE_BLOCK_PXN | PTE_BLOCK_UXN
122 .virt = 0x40000000UL,
123 .phys = 0x40000000UL,
124 .size = PHYS_SDRAM_SIZE,
125 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
126 PTE_BLOCK_OUTER_SHARE
127 #ifdef PHYS_SDRAM_2_SIZE
130 .virt = 0x100000000UL,
131 .phys = 0x100000000UL,
132 .size = PHYS_SDRAM_2_SIZE,
133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_OUTER_SHARE
137 /* List terminator */
142 struct mm_region *mem_map = imx8m_mem_map;
144 void enable_caches(void)
147 * If OPTEE runs, remove OPTEE memory from MMU table to
148 * avoid speculative prefetch. OPTEE runs at the top of
149 * the first memory bank
152 imx8m_mem_map[5].size -= rom_pointer[1];
158 static u32 get_cpu_variant_type(u32 type)
160 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
161 struct fuse_bank *bank = &ocotp->bank[1];
162 struct fuse_bank1_regs *fuse =
163 (struct fuse_bank1_regs *)bank->fuse_regs;
165 u32 value = readl(&fuse->tester4);
167 if (type == MXC_CPU_IMX8MM) {
168 switch (value & 0x3) {
170 if (value & 0x1c0000)
171 return MXC_CPU_IMX8MMDL;
173 return MXC_CPU_IMX8MMD;
175 if (value & 0x1c0000)
176 return MXC_CPU_IMX8MMSL;
178 return MXC_CPU_IMX8MMS;
180 if (value & 0x1c0000)
181 return MXC_CPU_IMX8MML;
189 u32 get_cpu_rev(void)
191 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
192 u32 reg = readl(&ana_pll->digprog);
193 u32 type = (reg >> 16) & 0xff;
194 u32 major_low = (reg >> 8) & 0xff;
200 if (major_low == 0x42) {
201 return (MXC_CPU_IMX8MN << 12) | reg;
202 } else if (major_low == 0x41) {
203 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
205 if (reg == CHIP_REV_1_0) {
207 * For B0 chip, the DIGPROG is not updated,
208 * it is still TO1.0. we have to check ROM
209 * version or OCOTP_READ_FUSE_DATA.
210 * 0xff0055aa is magic number for B1.
212 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
216 readl((void __iomem *)ROM_VERSION_A0);
217 if (rom_version != CHIP_REV_1_0) {
218 rom_version = readl((void __iomem *)ROM_VERSION_B0);
219 if (rom_version == CHIP_REV_2_0)
226 return (type << 12) | reg;
229 static void imx_set_wdog_powerdown(bool enable)
231 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
232 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
233 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
235 /* Write to the PDE (Power Down Enable) bit */
236 writew(enable, &wdog1->wmcr);
237 writew(enable, &wdog2->wmcr);
238 writew(enable, &wdog3->wmcr);
241 int arch_cpu_init_dm(void)
246 if (CONFIG_IS_ENABLED(CLK)) {
247 ret = uclass_get_device_by_name(UCLASS_CLK,
248 "clock-controller@30380000",
251 printf("Failed to find clock node. Check device tree\n");
259 int arch_cpu_init(void)
261 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
263 * ROM might disable clock for SCTR,
264 * enable the clock before timer_init.
266 if (IS_ENABLED(CONFIG_SPL_BUILD))
267 clock_enable(CCGR_SCTR, 1);
269 * Init timer at very early state, because sscg pll setting
274 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
276 imx_set_wdog_powerdown(false);
280 clock_enable(CCGR_OCOTP, 1);
281 if (readl(&ocotp->ctrl) & 0x200)
282 writel(0x200, &ocotp->ctrl_clr);
288 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
289 struct rom_api *g_rom_api = (struct rom_api *)0x980;
291 enum boot_device get_boot_device(void)
293 volatile gd_t *pgd = gd;
298 enum boot_device boot_dev = SD1_BOOT;
300 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
301 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
304 if (ret != ROM_API_OKAY) {
305 puts("ROMAPI: failure at query_boot_info\n");
309 boot_type = boot >> 16;
310 boot_instance = (boot >> 8) & 0xff;
314 boot_dev = boot_instance + SD1_BOOT;
316 case BT_DEV_TYPE_MMC:
317 boot_dev = boot_instance + MMC1_BOOT;
319 case BT_DEV_TYPE_NAND:
320 boot_dev = NAND_BOOT;
322 case BT_DEV_TYPE_FLEXSPINOR:
323 boot_dev = QSPI_BOOT;
325 case BT_DEV_TYPE_USB:
336 bool is_usb_boot(void)
338 return get_boot_device() == USB_BOOT;
341 #ifdef CONFIG_OF_SYSTEM_SETUP
342 int ft_system_setup(void *blob, bd_t *bd)
348 /* Disable the CPU idle for A0 chip since the HW does not support it */
349 if (is_soc_rev(CHIP_REV_1_0)) {
350 static const char * const nodes_path[] = {
357 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
358 nodeoff = fdt_path_offset(blob, nodes_path[i]);
360 continue; /* Not found, skip it */
362 printf("Found %s node\n", nodes_path[i]);
364 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
366 printf("Unable to update property %s:%s, err=%s\n",
367 nodes_path[i], "status", fdt_strerror(rc));
371 printf("Remove %s:%s\n", nodes_path[i],
380 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
381 void reset_cpu(ulong addr)
383 struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
386 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
388 /* Clear WDA to trigger WDOG_B immediately */
389 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
393 * spin for .5 seconds before reset