arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/hab.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/syscounter.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/armv8/mmu.h>
  21 #include <dm/uclass.h>
  22 #include <efi_loader.h>
  23 #include <env.h>
  24 #include <env_internal.h>
  25 #include <errno.h>
  26 #include <fdt_support.h>
  27 #include <fsl_wdog.h>
  28 #include <imx_sip.h>
  29 #include <linux/arm-smccc.h>
  30 #include <linux/bitops.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #if defined(CONFIG_IMX_HAB)
  35 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  36         .bank = 1,
  37         .word = 3,
  38 };
  39 #endif
  40
  41 int timer_init(void)
  42 {
  43 #ifdef CONFIG_SPL_BUILD
  44         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  45         unsigned long freq = readl(&sctr->cntfid0);
  46
  47         /* Update with accurate clock frequency */
  48         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  49
  50         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  51                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  52 #endif
  53
  54         gd->arch.tbl = 0;
  55         gd->arch.tbu = 0;
  56
  57         return 0;
  58 }
  59
  60 void enable_tzc380(void)
  61 {
  62         struct iomuxc_gpr_base_regs *gpr =
  63                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  64
  65         /* Enable TZASC and lock setting */
  66         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  67         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  68         if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  69                 setbits_le32(&gpr->gpr[10], BIT(1));
  70         /*
  71          * set Region 0 attribute to allow secure and non-secure
  72          * read/write permission. Found some masters like usb dwc3
  73          * controllers can't work with secure memory.
  74          */
  75         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  76 }
  77
  78 void set_wdog_reset(struct wdog_regs *wdog)
  79 {
  80         /*
  81          * Output WDOG_B signal to reset external pmic or POR_B decided by
  82          * the board design. Without external reset, the peripherals/DDR/
  83          * PMIC are not reset, that may cause system working abnormal.
  84          * WDZST bit is write-once only bit. Align this bit in kernel,
  85          * otherwise kernel code will have no chance to set this bit.
  86          */
  87         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  88 }
  89
  90 static struct mm_region imx8m_mem_map[] = {
  91         {
  92                 /* ROM */
  93                 .virt = 0x0UL,
  94                 .phys = 0x0UL,
  95                 .size = 0x100000UL,
  96                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  97                          PTE_BLOCK_OUTER_SHARE
  98         }, {
  99                 /* CAAM */
 100                 .virt = 0x100000UL,
 101                 .phys = 0x100000UL,
 102                 .size = 0x8000UL,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 104                          PTE_BLOCK_NON_SHARE |
 105                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 106         }, {
 107                 /* TCM */
 108                 .virt = 0x7C0000UL,
 109                 .phys = 0x7C0000UL,
 110                 .size = 0x80000UL,
 111                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 112                          PTE_BLOCK_NON_SHARE |
 113                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 114         }, {
 115                 /* OCRAM */
 116                 .virt = 0x900000UL,
 117                 .phys = 0x900000UL,
 118                 .size = 0x200000UL,
 119                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 120                          PTE_BLOCK_OUTER_SHARE
 121         }, {
 122                 /* AIPS */
 123                 .virt = 0xB00000UL,
 124                 .phys = 0xB00000UL,
 125                 .size = 0x3f500000UL,
 126                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 127                          PTE_BLOCK_NON_SHARE |
 128                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 129         }, {
 130                 /* DRAM1 */
 131                 .virt = 0x40000000UL,
 132                 .phys = 0x40000000UL,
 133                 .size = PHYS_SDRAM_SIZE,
 134                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 135                          PTE_BLOCK_OUTER_SHARE
 136 #ifdef PHYS_SDRAM_2_SIZE
 137         }, {
 138                 /* DRAM2 */
 139                 .virt = 0x100000000UL,
 140                 .phys = 0x100000000UL,
 141                 .size = PHYS_SDRAM_2_SIZE,
 142                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 143                          PTE_BLOCK_OUTER_SHARE
 144 #endif
 145         }, {
 146                 /* empty entrie to split table entry 5 if needed when TEEs are used */
 147                 0,
 148         }, {
 149                 /* List terminator */
 150                 0,
 151         }
 152 };
 153
 154 struct mm_region *mem_map = imx8m_mem_map;
 155
 156 void enable_caches(void)
 157 {
 158         /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
 159         if (rom_pointer[1]) {
 160                 /*
 161                  * TEE are loaded, So the ddr bank structures
 162                  * have been modified update mmu table accordingly
 163                  */
 164                 int i = 0;
 165                 /*
 166                  * please make sure that entry initial value matches
 167                  * imx8m_mem_map for DRAM1
 168                  */
 169                 int entry = 5;
 170                 u64 attrs = imx8m_mem_map[entry].attrs;
 171
 172                 while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
 173                         if (gd->bd->bi_dram[i].start == 0)
 174                                 break;
 175                         imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
 176                         imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
 177                         imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
 178                         imx8m_mem_map[entry].attrs = attrs;
 179                         debug("Added memory mapping (%d): %llx %llx\n", entry,
 180                               imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
 181                         i++; entry++;
 182                 }
 183         }
 184
 185         icache_enable();
 186         dcache_enable();
 187 }
 188
 189 __weak int board_phys_sdram_size(phys_size_t *size)
 190 {
 191         if (!size)
 192                 return -EINVAL;
 193
 194         *size = PHYS_SDRAM_SIZE;
 195         return 0;
 196 }
 197
 198 int dram_init(void)
 199 {
 200         phys_size_t sdram_size;
 201         int ret;
 202
 203         ret = board_phys_sdram_size(&sdram_size);
 204         if (ret)
 205                 return ret;
 206
 207         /* rom_pointer[1] contains the size of TEE occupies */
 208         if (rom_pointer[1])
 209                 gd->ram_size = sdram_size - rom_pointer[1];
 210         else
 211                 gd->ram_size = sdram_size;
 212
 213 #ifdef PHYS_SDRAM_2_SIZE
 214         gd->ram_size += PHYS_SDRAM_2_SIZE;
 215 #endif
 216
 217         return 0;
 218 }
 219
 220 int dram_init_banksize(void)
 221 {
 222         int bank = 0;
 223         int ret;
 224         phys_size_t sdram_size;
 225
 226         ret = board_phys_sdram_size(&sdram_size);
 227         if (ret)
 228                 return ret;
 229
 230         gd->bd->bi_dram[bank].start = PHYS_SDRAM;
 231         if (rom_pointer[1]) {
 232                 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 233                 phys_size_t optee_size = (size_t)rom_pointer[1];
 234
 235                 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
 236                 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
 237                         if (++bank >= CONFIG_NR_DRAM_BANKS) {
 238                                 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 239                                 return -1;
 240                         }
 241
 242                         gd->bd->bi_dram[bank].start = optee_start + optee_size;
 243                         gd->bd->bi_dram[bank].size = PHYS_SDRAM +
 244                                 sdram_size - gd->bd->bi_dram[bank].start;
 245                 }
 246         } else {
 247                 gd->bd->bi_dram[bank].size = sdram_size;
 248         }
 249
 250 #ifdef PHYS_SDRAM_2_SIZE
 251         if (++bank >= CONFIG_NR_DRAM_BANKS) {
 252                 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
 253                 return -1;
 254         }
 255         gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
 256         gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
 257 #endif
 258
 259         return 0;
 260 }
 261
 262 phys_size_t get_effective_memsize(void)
 263 {
 264         /* return the first bank as effective memory */
 265         if (rom_pointer[1])
 266                 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
 267
 268 #ifdef PHYS_SDRAM_2_SIZE
 269         return gd->ram_size - PHYS_SDRAM_2_SIZE;
 270 #else
 271         return gd->ram_size;
 272 #endif
 273 }
 274
 275 static u32 get_cpu_variant_type(u32 type)
 276 {
 277         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 278         struct fuse_bank *bank = &ocotp->bank[1];
 279         struct fuse_bank1_regs *fuse =
 280                 (struct fuse_bank1_regs *)bank->fuse_regs;
 281
 282         u32 value = readl(&fuse->tester4);
 283
 284         if (type == MXC_CPU_IMX8MQ) {
 285                 if ((value & 0x3) == 0x2)
 286                         return MXC_CPU_IMX8MD;
 287                 else if (value & 0x200000)
 288                         return MXC_CPU_IMX8MQL;
 289
 290         } else if (type == MXC_CPU_IMX8MM) {
 291                 switch (value & 0x3) {
 292                 case 2:
 293                         if (value & 0x1c0000)
 294                                 return MXC_CPU_IMX8MMDL;
 295                         else
 296                                 return MXC_CPU_IMX8MMD;
 297                 case 3:
 298                         if (value & 0x1c0000)
 299                                 return MXC_CPU_IMX8MMSL;
 300                         else
 301                                 return MXC_CPU_IMX8MMS;
 302                 default:
 303                         if (value & 0x1c0000)
 304                                 return MXC_CPU_IMX8MML;
 305                         break;
 306                 }
 307         } else if (type == MXC_CPU_IMX8MN) {
 308                 switch (value & 0x3) {
 309                 case 2:
 310                         if (value & 0x1000000)
 311                                 return MXC_CPU_IMX8MNDL;
 312                         else
 313                                 return MXC_CPU_IMX8MND;
 314                 case 3:
 315                         if (value & 0x1000000)
 316                                 return MXC_CPU_IMX8MNSL;
 317                         else
 318                                 return MXC_CPU_IMX8MNS;
 319                 default:
 320                         if (value & 0x1000000)
 321                                 return MXC_CPU_IMX8MNL;
 322                         break;
 323                 }
 324         } else if (type == MXC_CPU_IMX8MP) {
 325                 u32 value0 = readl(&fuse->tester3);
 326                 u32 flag = 0;
 327
 328                 if ((value0 & 0xc0000) == 0x80000)
 329                         return MXC_CPU_IMX8MPD;
 330
 331                         /* vpu disabled */
 332                 if ((value0 & 0x43000000) == 0x43000000)
 333                         flag = 1;
 334
 335                 /* npu disabled*/
 336                 if ((value & 0x8) == 0x8)
 337                         flag |= (1 << 1);
 338
 339                 /* isp disabled */
 340                 if ((value & 0x3) == 0x3)
 341                         flag |= (1 << 2);
 342
 343                 switch (flag) {
 344                 case 7:
 345                         return MXC_CPU_IMX8MPL;
 346                 case 2:
 347                         return MXC_CPU_IMX8MP6;
 348                 default:
 349                         break;
 350                 }
 351
 352         }
 353
 354         return type;
 355 }
 356
 357 u32 get_cpu_rev(void)
 358 {
 359         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 360         u32 reg = readl(&ana_pll->digprog);
 361         u32 type = (reg >> 16) & 0xff;
 362         u32 major_low = (reg >> 8) & 0xff;
 363         u32 rom_version;
 364
 365         reg &= 0xff;
 366
 367         /* iMX8MP */
 368         if (major_low == 0x43) {
 369                 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
 370         } else if (major_low == 0x42) {
 371                 /* iMX8MN */
 372                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
 373         } else if (major_low == 0x41) {
 374                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 375         } else {
 376                 if (reg == CHIP_REV_1_0) {
 377                         /*
 378                          * For B0 chip, the DIGPROG is not updated,
 379                          * it is still TO1.0. we have to check ROM
 380                          * version or OCOTP_READ_FUSE_DATA.
 381                          * 0xff0055aa is magic number for B1.
 382                          */
 383                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 384                                 reg = CHIP_REV_2_1;
 385                         } else {
 386                                 rom_version =
 387                                         readl((void __iomem *)ROM_VERSION_A0);
 388                                 if (rom_version != CHIP_REV_1_0) {
 389                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 390                                         rom_version &= 0xff;
 391                                         if (rom_version == CHIP_REV_2_0)
 392                                                 reg = CHIP_REV_2_0;
 393                                 }
 394                         }
 395                 }
 396
 397                 type = get_cpu_variant_type(type);
 398         }
 399
 400         return (type << 12) | reg;
 401 }
 402
 403 static void imx_set_wdog_powerdown(bool enable)
 404 {
 405         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 406         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 407         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 408
 409         /* Write to the PDE (Power Down Enable) bit */
 410         writew(enable, &wdog1->wmcr);
 411         writew(enable, &wdog2->wmcr);
 412         writew(enable, &wdog3->wmcr);
 413 }
 414
 415 int arch_cpu_init_dm(void)
 416 {
 417         struct udevice *dev;
 418         int ret;
 419
 420         if (CONFIG_IS_ENABLED(CLK)) {
 421                 ret = uclass_get_device_by_name(UCLASS_CLK,
 422                                                 "clock-controller@30380000",
 423                                                 &dev);
 424                 if (ret < 0) {
 425                         printf("Failed to find clock node. Check device tree\n");
 426                         return ret;
 427                 }
 428         }
 429
 430         return 0;
 431 }
 432
 433 int arch_cpu_init(void)
 434 {
 435         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 436         /*
 437          * ROM might disable clock for SCTR,
 438          * enable the clock before timer_init.
 439          */
 440         if (IS_ENABLED(CONFIG_SPL_BUILD))
 441                 clock_enable(CCGR_SCTR, 1);
 442         /*
 443          * Init timer at very early state, because sscg pll setting
 444          * will use it
 445          */
 446         timer_init();
 447
 448         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 449                 clock_init();
 450                 imx_set_wdog_powerdown(false);
 451
 452                 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
 453                     is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
 454                     is_imx8mnsl() || is_imx8mpd()) {
 455                         /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
 456                         struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
 457                         struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
 458                         struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
 459                         struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
 460
 461                         writel(0x1, &pgc_core2->pgcr);
 462                         writel(0x1, &pgc_core3->pgcr);
 463                         if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
 464                                 writel(0x1, &pgc_core1->pgcr);
 465                                 writel(0xE, &gpc->cpu_pgc_dn_trg);
 466                         } else {
 467                                 writel(0xC, &gpc->cpu_pgc_dn_trg);
 468                         }
 469                 }
 470         }
 471
 472         if (is_imx8mq()) {
 473                 clock_enable(CCGR_OCOTP, 1);
 474                 if (readl(&ocotp->ctrl) & 0x200)
 475                         writel(0x200, &ocotp->ctrl_clr);
 476         }
 477
 478         return 0;
 479 }
 480
 481 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 482 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 483
 484 enum boot_device get_boot_device(void)
 485 {
 486         volatile gd_t *pgd = gd;
 487         int ret;
 488         u32 boot;
 489         u16 boot_type;
 490         u8 boot_instance;
 491         enum boot_device boot_dev = SD1_BOOT;
 492
 493         ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
 494                                           ((uintptr_t)&boot) ^ QUERY_BT_DEV);
 495         gd = pgd;
 496
 497         if (ret != ROM_API_OKAY) {
 498                 puts("ROMAPI: failure at query_boot_info\n");
 499                 return -1;
 500         }
 501
 502         boot_type = boot >> 16;
 503         boot_instance = (boot >> 8) & 0xff;
 504
 505         switch (boot_type) {
 506         case BT_DEV_TYPE_SD:
 507                 boot_dev = boot_instance + SD1_BOOT;
 508                 break;
 509         case BT_DEV_TYPE_MMC:
 510                 boot_dev = boot_instance + MMC1_BOOT;
 511                 break;
 512         case BT_DEV_TYPE_NAND:
 513                 boot_dev = NAND_BOOT;
 514                 break;
 515         case BT_DEV_TYPE_FLEXSPINOR:
 516                 boot_dev = QSPI_BOOT;
 517                 break;
 518         case BT_DEV_TYPE_USB:
 519                 boot_dev = USB_BOOT;
 520                 break;
 521         default:
 522                 break;
 523         }
 524
 525         return boot_dev;
 526 }
 527 #endif
 528
 529 bool is_usb_boot(void)
 530 {
 531         return get_boot_device() == USB_BOOT;
 532 }
 533
 534 #ifdef CONFIG_OF_SYSTEM_SETUP
 535 bool check_fdt_new_path(void *blob)
 536 {
 537         const char *soc_path = "/soc@0";
 538         int nodeoff;
 539
 540         nodeoff = fdt_path_offset(blob, soc_path);
 541         if (nodeoff < 0)
 542                 return false;
 543
 544         return true;
 545 }
 546
 547 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
 548 {
 549         int i = 0;
 550         int rc;
 551         int nodeoff;
 552         const char *status = "disabled";
 553
 554         for (i = 0; i < size_array; i++) {
 555                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
 556                 if (nodeoff < 0)
 557                         continue; /* Not found, skip it */
 558
 559                 printf("Found %s node\n", nodes_path[i]);
 560
 561 add_status:
 562                 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
 563                 if (rc) {
 564                         if (rc == -FDT_ERR_NOSPACE) {
 565                                 rc = fdt_increase_size(blob, 512);
 566                                 if (!rc)
 567                                         goto add_status;
 568                         }
 569                         printf("Unable to update property %s:%s, err=%s\n",
 570                                nodes_path[i], "status", fdt_strerror(rc));
 571                 } else {
 572                         printf("Modify %s:%s disabled\n",
 573                                nodes_path[i], "status");
 574                 }
 575         }
 576
 577         return 0;
 578 }
 579
 580 #ifdef CONFIG_IMX8MQ
 581 bool check_dcss_fused(void)
 582 {
 583         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 584         struct fuse_bank *bank = &ocotp->bank[1];
 585         struct fuse_bank1_regs *fuse =
 586                 (struct fuse_bank1_regs *)bank->fuse_regs;
 587         u32 value = readl(&fuse->tester4);
 588
 589         if (value & 0x4000000)
 590                 return true;
 591
 592         return false;
 593 }
 594
 595 static int disable_mipi_dsi_nodes(void *blob)
 596 {
 597         static const char * const nodes_path[] = {
 598                 "/mipi_dsi@30A00000",
 599                 "/mipi_dsi_bridge@30A00000",
 600                 "/dsi_phy@30A00300",
 601                 "/soc@0/bus@30800000/mipi_dsi@30a00000",
 602                 "/soc@0/bus@30800000/dphy@30a00300"
 603         };
 604
 605         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 606 }
 607
 608 static int disable_dcss_nodes(void *blob)
 609 {
 610         static const char * const nodes_path[] = {
 611                 "/dcss@0x32e00000",
 612                 "/dcss@32e00000",
 613                 "/hdmi@32c00000",
 614                 "/hdmi_cec@32c33800",
 615                 "/hdmi_drm@32c00000",
 616                 "/display-subsystem",
 617                 "/sound-hdmi",
 618                 "/sound-hdmi-arc",
 619                 "/soc@0/bus@32c00000/display-controller@32e00000",
 620                 "/soc@0/bus@32c00000/hdmi@32c00000",
 621         };
 622
 623         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
 624 }
 625
 626 static int check_mipi_dsi_nodes(void *blob)
 627 {
 628         static const char * const lcdif_path[] = {
 629                 "/lcdif@30320000",
 630                 "/soc@0/bus@30000000/lcdif@30320000"
 631         };
 632         static const char * const mipi_dsi_path[] = {
 633                 "/mipi_dsi@30A00000",
 634                 "/soc@0/bus@30800000/mipi_dsi@30a00000"
 635         };
 636         static const char * const lcdif_ep_path[] = {
 637                 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
 638                 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint"
 639         };
 640         static const char * const mipi_dsi_ep_path[] = {
 641                 "/mipi_dsi@30A00000/port@1/endpoint",
 642                 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint"
 643         };
 644
 645         int lookup_node;
 646         int nodeoff;
 647         bool new_path = check_fdt_new_path(blob);
 648         int i = new_path ? 1 : 0;
 649
 650         nodeoff = fdt_path_offset(blob, lcdif_path[i]);
 651         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
 652                 /*
 653                  * If can't find lcdif node or lcdif node is disabled,
 654                  * then disable all mipi dsi, since they only can input
 655                  * from DCSS
 656                  */
 657                 return disable_mipi_dsi_nodes(blob);
 658         }
 659
 660         nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
 661         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
 662                 return 0;
 663
 664         nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
 665         if (nodeoff < 0) {
 666                 /*
 667                  * If can't find lcdif endpoint, then disable all mipi dsi,
 668                  * since they only can input from DCSS
 669                  */
 670                 return disable_mipi_dsi_nodes(blob);
 671         }
 672
 673         lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
 674         nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
 675
 676         if (nodeoff > 0 && nodeoff == lookup_node)
 677                 return 0;
 678
 679         return disable_mipi_dsi_nodes(blob);
 680 }
 681 #endif
 682
 683 int disable_vpu_nodes(void *blob)
 684 {
 685         static const char * const nodes_path_8mq[] = {
 686                 "/vpu@38300000",
 687                 "/soc@0/vpu@38300000"
 688         };
 689
 690         static const char * const nodes_path_8mm[] = {
 691                 "/vpu_g1@38300000",
 692                 "/vpu_g2@38310000",
 693                 "/vpu_h1@38320000"
 694         };
 695
 696         static const char * const nodes_path_8mp[] = {
 697                 "/vpu_g1@38300000",
 698                 "/vpu_g2@38310000",
 699                 "/vpu_vc8000e@38320000"
 700         };
 701
 702         if (is_imx8mq())
 703                 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
 704         else if (is_imx8mm())
 705                 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
 706         else if (is_imx8mp())
 707                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 708         else
 709                 return -EPERM;
 710 }
 711
 712 int disable_gpu_nodes(void *blob)
 713 {
 714         static const char * const nodes_path_8mn[] = {
 715                 "/gpu@38000000"
 716         };
 717
 718         return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
 719 }
 720
 721 int disable_npu_nodes(void *blob)
 722 {
 723         static const char * const nodes_path_8mp[] = {
 724                 "/vipsi@38500000"
 725         };
 726
 727         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 728 }
 729
 730 int disable_isp_nodes(void *blob)
 731 {
 732         static const char * const nodes_path_8mp[] = {
 733                 "/soc@0/bus@32c00000/camera/isp@32e10000",
 734                 "/soc@0/bus@32c00000/camera/isp@32e20000"
 735         };
 736
 737         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 738 }
 739
 740 int disable_dsp_nodes(void *blob)
 741 {
 742         static const char * const nodes_path_8mp[] = {
 743                 "/dsp@3b6e8000"
 744         };
 745
 746         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
 747 }
 748
 749 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
 750 {
 751         static const char * const nodes_path[] = {
 752                 "/cpus/cpu@1",
 753                 "/cpus/cpu@2",
 754                 "/cpus/cpu@3",
 755         };
 756         u32 i = 0;
 757         int rc;
 758         int nodeoff;
 759
 760         if (disabled_cores > 3)
 761                 return -EINVAL;
 762
 763         i = 3 - disabled_cores;
 764
 765         for (; i < 3; i++) {
 766                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
 767                 if (nodeoff < 0)
 768                         continue; /* Not found, skip it */
 769
 770                 debug("Found %s node\n", nodes_path[i]);
 771
 772                 rc = fdt_del_node(blob, nodeoff);
 773                 if (rc < 0) {
 774                         printf("Unable to delete node %s, err=%s\n",
 775                                nodes_path[i], fdt_strerror(rc));
 776                 } else {
 777                         printf("Delete node %s\n", nodes_path[i]);
 778                 }
 779         }
 780
 781         return 0;
 782 }
 783
 784 int ft_system_setup(void *blob, struct bd_info *bd)
 785 {
 786 #ifdef CONFIG_IMX8MQ
 787         int i = 0;
 788         int rc;
 789         int nodeoff;
 790
 791         if (get_boot_device() == USB_BOOT) {
 792                 disable_dcss_nodes(blob);
 793
 794                 bool new_path = check_fdt_new_path(blob);
 795                 int v = new_path ? 1 : 0;
 796                 static const char * const usb_dwc3_path[] = {
 797                         "/usb@38100000/dwc3",
 798                         "/soc@0/usb@38100000"
 799                 };
 800
 801                 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
 802                 if (nodeoff >= 0) {
 803                         const char *speed = "high-speed";
 804
 805                         printf("Found %s node\n", usb_dwc3_path[v]);
 806
 807 usb_modify_speed:
 808
 809                         rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
 810                         if (rc) {
 811                                 if (rc == -FDT_ERR_NOSPACE) {
 812                                         rc = fdt_increase_size(blob, 512);
 813                                         if (!rc)
 814                                                 goto usb_modify_speed;
 815                                 }
 816                                 printf("Unable to set property %s:%s, err=%s\n",
 817                                        usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
 818                         } else {
 819                                 printf("Modify %s:%s = %s\n",
 820                                        usb_dwc3_path[v], "maximum-speed", speed);
 821                         }
 822                 } else {
 823                         printf("Can't found %s node\n", usb_dwc3_path[v]);
 824                 }
 825         }
 826
 827         /* Disable the CPU idle for A0 chip since the HW does not support it */
 828         if (is_soc_rev(CHIP_REV_1_0)) {
 829                 static const char * const nodes_path[] = {
 830                         "/cpus/cpu@0",
 831                         "/cpus/cpu@1",
 832                         "/cpus/cpu@2",
 833                         "/cpus/cpu@3",
 834                 };
 835
 836                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 837                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 838                         if (nodeoff < 0)
 839                                 continue; /* Not found, skip it */
 840
 841                         debug("Found %s node\n", nodes_path[i]);
 842
 843                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 844                         if (rc == -FDT_ERR_NOTFOUND)
 845                                 continue;
 846                         if (rc) {
 847                                 printf("Unable to update property %s:%s, err=%s\n",
 848                                        nodes_path[i], "status", fdt_strerror(rc));
 849                                 return rc;
 850                         }
 851
 852                         debug("Remove %s:%s\n", nodes_path[i],
 853                                "cpu-idle-states");
 854                 }
 855         }
 856
 857         if (is_imx8mql()) {
 858                 disable_vpu_nodes(blob);
 859                 if (check_dcss_fused()) {
 860                         printf("DCSS is fused\n");
 861                         disable_dcss_nodes(blob);
 862                         check_mipi_dsi_nodes(blob);
 863                 }
 864         }
 865
 866         if (is_imx8md())
 867                 disable_cpu_nodes(blob, 2);
 868
 869 #elif defined(CONFIG_IMX8MM)
 870         if (is_imx8mml() || is_imx8mmdl() ||  is_imx8mmsl())
 871                 disable_vpu_nodes(blob);
 872
 873         if (is_imx8mmd() || is_imx8mmdl())
 874                 disable_cpu_nodes(blob, 2);
 875         else if (is_imx8mms() || is_imx8mmsl())
 876                 disable_cpu_nodes(blob, 3);
 877
 878 #elif defined(CONFIG_IMX8MN)
 879         if (is_imx8mnl() || is_imx8mndl() ||  is_imx8mnsl())
 880                 disable_gpu_nodes(blob);
 881
 882         if (is_imx8mnd() || is_imx8mndl())
 883                 disable_cpu_nodes(blob, 2);
 884         else if (is_imx8mns() || is_imx8mnsl())
 885                 disable_cpu_nodes(blob, 3);
 886
 887 #elif defined(CONFIG_IMX8MP)
 888         if (is_imx8mpl())
 889                 disable_vpu_nodes(blob);
 890
 891         if (is_imx8mpl() || is_imx8mp6())
 892                 disable_npu_nodes(blob);
 893
 894         if (is_imx8mpl())
 895                 disable_isp_nodes(blob);
 896
 897         if (is_imx8mpl() || is_imx8mp6())
 898                 disable_dsp_nodes(blob);
 899
 900         if (is_imx8mpd())
 901                 disable_cpu_nodes(blob, 2);
 902 #endif
 903
 904         return 0;
 905 }
 906 #endif
 907
 908 #if !CONFIG_IS_ENABLED(SYSRESET)
 909 void reset_cpu(ulong addr)
 910 {
 911         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 912
 913         /* Clear WDA to trigger WDOG_B immediately */
 914         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
 915
 916         while (1) {
 917                 /*
 918                  * spin for .5 seconds before reset
 919                  */
 920         }
 921 }
 922 #endif
 923
 924 #if defined(CONFIG_ARCH_MISC_INIT)
 925 static void acquire_buildinfo(void)
 926 {
 927         u64 atf_commit = 0;
 928         struct arm_smccc_res res;
 929
 930         /* Get ARM Trusted Firmware commit id */
 931         arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
 932                       0, 0, 0, 0, 0, 0, &res);
 933         atf_commit = res.a0;
 934         if (atf_commit == 0xffffffff) {
 935                 debug("ATF does not support build info\n");
 936                 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
 937         }
 938
 939         printf("\n BuildInfo:\n  - ATF %s\n\n", (char *)&atf_commit);
 940 }
 941
 942 int arch_misc_init(void)
 943 {
 944         acquire_buildinfo();
 945
 946         return 0;
 947 }
 948 #endif
 949
 950 void imx_tmu_arch_init(void *reg_base)
 951 {
 952         if (is_imx8mm() || is_imx8mn()) {
 953                 /* Load TCALIV and TASR from fuses */
 954                 struct ocotp_regs *ocotp =
 955                         (struct ocotp_regs *)OCOTP_BASE_ADDR;
 956                 struct fuse_bank *bank = &ocotp->bank[3];
 957                 struct fuse_bank3_regs *fuse =
 958                         (struct fuse_bank3_regs *)bank->fuse_regs;
 959
 960                 u32 tca_rt, tca_hr, tca_en;
 961                 u32 buf_vref, buf_slope;
 962
 963                 tca_rt = fuse->ana0 & 0xFF;
 964                 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
 965                 tca_en = (fuse->ana0 & 0x2000000) >> 25;
 966
 967                 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
 968                 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
 969
 970                 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
 971                 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
 972                        (ulong)reg_base + 0x30);
 973         }
 974 #ifdef CONFIG_IMX8MP
 975         /* Load TCALIV0/1/m40 and TRIM from fuses */
 976         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 977         struct fuse_bank *bank = &ocotp->bank[38];
 978         struct fuse_bank38_regs *fuse =
 979                 (struct fuse_bank38_regs *)bank->fuse_regs;
 980         struct fuse_bank *bank2 = &ocotp->bank[39];
 981         struct fuse_bank39_regs *fuse2 =
 982                 (struct fuse_bank39_regs *)bank2->fuse_regs;
 983         u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
 984         u32 reg;
 985         u32 tca40[2], tca25[2], tca105[2];
 986
 987         /* For blank sample */
 988         if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
 989             !fuse->ana_trim4 && !fuse2->ana_trim5) {
 990                 /* Use a default 25C binary codes */
 991                 tca25[0] = 1596;
 992                 tca25[1] = 1596;
 993                 writel(tca25[0], (ulong)reg_base + 0x30);
 994                 writel(tca25[1], (ulong)reg_base + 0x34);
 995                 return;
 996         }
 997
 998         buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
 999         buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1000         bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1001         bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1002         vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1003         writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1004
1005         reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
1006         writel(reg, (ulong)reg_base + 0x3c);
1007
1008         tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1009         tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1010         tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1011         tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1012         tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1013         tca25[1] = fuse2->ana_trim5 & 0xFFF;
1014         tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1015
1016         /* use 25c for 1p calibration */
1017         writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1018         writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1019         writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1020 #endif
1021 }
1022
1023 #if defined(CONFIG_SPL_BUILD)
1024 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1025 bool serror_need_skip = true;
1026
1027 void do_error(struct pt_regs *pt_regs, unsigned int esr)
1028 {
1029         /*
1030          * If stack is still in ROM reserved OCRAM not switch to SPL,
1031          * it is the ROM SError
1032          */
1033         ulong sp;
1034
1035         asm volatile("mov %0, sp" : "=r"(sp) : );
1036
1037         if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1038                 /* Check for ERR050342, imx8mq HDCP enabled parts */
1039                 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1040                         serror_need_skip = false;
1041                         return; /* Do nothing skip the SError in ROM */
1042                 }
1043
1044                 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1045                 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1046                         serror_need_skip = false;
1047                         return; /* Do nothing skip the SError in ROM */
1048                 }
1049         }
1050
1051         efi_restore_gd();
1052         printf("\"Error\" handler, esr 0x%08x\n", esr);
1053         show_regs(pt_regs);
1054         panic("Resetting CPU ...\n");
1055 }
1056 #endif
1057 #endif
1058
1059 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1060 enum env_location env_get_location(enum env_operation op, int prio)
1061 {
1062         enum boot_device dev = get_boot_device();
1063         enum env_location env_loc = ENVL_UNKNOWN;
1064
1065         if (prio)
1066                 return env_loc;
1067
1068         switch (dev) {
1069 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1070         case QSPI_BOOT:
1071                 env_loc = ENVL_SPI_FLASH;
1072                 break;
1073 #endif
1074 #ifdef CONFIG_ENV_IS_IN_NAND
1075         case NAND_BOOT:
1076                 env_loc = ENVL_NAND;
1077                 break;
1078 #endif
1079 #ifdef CONFIG_ENV_IS_IN_MMC
1080         case SD1_BOOT:
1081         case SD2_BOOT:
1082         case SD3_BOOT:
1083         case MMC1_BOOT:
1084         case MMC2_BOOT:
1085         case MMC3_BOOT:
1086                 env_loc =  ENVL_MMC;
1087                 break;
1088 #endif
1089         default:
1090 #if defined(CONFIG_ENV_IS_NOWHERE)
1091                 env_loc = ENVL_NOWHERE;
1092 #endif
1093                 break;
1094         }
1095
1096         return env_loc;
1097 }
1098
1099 #ifndef ENV_IS_EMBEDDED
1100 long long env_get_offset(long long defautl_offset)
1101 {
1102         enum boot_device dev = get_boot_device();
1103
1104         switch (dev) {
1105         case NAND_BOOT:
1106                 return (60 << 20);  /* 60MB offset for NAND */
1107         default:
1108                 break;
1109         }
1110
1111         return defautl_offset;
1112 }
1113 #endif
1114 #endif