1 // SPDX-License-Identifier: GPL-2.0+
5 * Peng Fan <peng.fan@nxp.com>
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/hab.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/syscounter.h>
17 #include <asm/armv8/mmu.h>
18 #include <dm/uclass.h>
20 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #if defined(CONFIG_IMX_HAB)
27 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
35 #ifdef CONFIG_SPL_BUILD
36 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
37 unsigned long freq = readl(&sctr->cntfid0);
39 /* Update with accurate clock frequency */
40 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
42 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
43 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
52 void enable_tzc380(void)
54 struct iomuxc_gpr_base_regs *gpr =
55 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
57 /* Enable TZASC and lock setting */
58 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
59 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
60 if (is_imx8mm() || is_imx8mn() || is_imx8mp())
61 setbits_le32(&gpr->gpr[10], BIT(1));
63 * set Region 0 attribute to allow secure and non-secure
64 * read/write permission. Found some masters like usb dwc3
65 * controllers can't work with secure memory.
67 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
70 void set_wdog_reset(struct wdog_regs *wdog)
73 * Output WDOG_B signal to reset external pmic or POR_B decided by
74 * the board design. Without external reset, the peripherals/DDR/
75 * PMIC are not reset, that may cause system working abnormal.
76 * WDZST bit is write-once only bit. Align this bit in kernel,
77 * otherwise kernel code will have no chance to set this bit.
79 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
82 static struct mm_region imx8m_mem_map[] = {
88 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
95 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
97 PTE_BLOCK_PXN | PTE_BLOCK_UXN
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN
111 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
112 PTE_BLOCK_OUTER_SHARE
117 .size = 0x3f500000UL,
118 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
119 PTE_BLOCK_NON_SHARE |
120 PTE_BLOCK_PXN | PTE_BLOCK_UXN
123 .virt = 0x40000000UL,
124 .phys = 0x40000000UL,
125 .size = PHYS_SDRAM_SIZE,
126 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
127 PTE_BLOCK_OUTER_SHARE
128 #ifdef PHYS_SDRAM_2_SIZE
131 .virt = 0x100000000UL,
132 .phys = 0x100000000UL,
133 .size = PHYS_SDRAM_2_SIZE,
134 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
135 PTE_BLOCK_OUTER_SHARE
138 /* List terminator */
143 struct mm_region *mem_map = imx8m_mem_map;
145 void enable_caches(void)
148 * If OPTEE runs, remove OPTEE memory from MMU table to
149 * avoid speculative prefetch. OPTEE runs at the top of
150 * the first memory bank
153 imx8m_mem_map[5].size -= rom_pointer[1];
159 static u32 get_cpu_variant_type(u32 type)
161 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
162 struct fuse_bank *bank = &ocotp->bank[1];
163 struct fuse_bank1_regs *fuse =
164 (struct fuse_bank1_regs *)bank->fuse_regs;
166 u32 value = readl(&fuse->tester4);
168 if (type == MXC_CPU_IMX8MM) {
169 switch (value & 0x3) {
171 if (value & 0x1c0000)
172 return MXC_CPU_IMX8MMDL;
174 return MXC_CPU_IMX8MMD;
176 if (value & 0x1c0000)
177 return MXC_CPU_IMX8MMSL;
179 return MXC_CPU_IMX8MMS;
181 if (value & 0x1c0000)
182 return MXC_CPU_IMX8MML;
190 u32 get_cpu_rev(void)
192 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
193 u32 reg = readl(&ana_pll->digprog);
194 u32 type = (reg >> 16) & 0xff;
195 u32 major_low = (reg >> 8) & 0xff;
201 if (major_low == 0x43) {
202 return (MXC_CPU_IMX8MP << 12) | reg;
203 } else if (major_low == 0x42) {
205 return (MXC_CPU_IMX8MN << 12) | reg;
206 } else if (major_low == 0x41) {
207 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
209 if (reg == CHIP_REV_1_0) {
211 * For B0 chip, the DIGPROG is not updated,
212 * it is still TO1.0. we have to check ROM
213 * version or OCOTP_READ_FUSE_DATA.
214 * 0xff0055aa is magic number for B1.
216 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
220 readl((void __iomem *)ROM_VERSION_A0);
221 if (rom_version != CHIP_REV_1_0) {
222 rom_version = readl((void __iomem *)ROM_VERSION_B0);
224 if (rom_version == CHIP_REV_2_0)
231 return (type << 12) | reg;
234 static void imx_set_wdog_powerdown(bool enable)
236 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
237 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
238 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
240 /* Write to the PDE (Power Down Enable) bit */
241 writew(enable, &wdog1->wmcr);
242 writew(enable, &wdog2->wmcr);
243 writew(enable, &wdog3->wmcr);
246 int arch_cpu_init_dm(void)
251 if (CONFIG_IS_ENABLED(CLK)) {
252 ret = uclass_get_device_by_name(UCLASS_CLK,
253 "clock-controller@30380000",
256 printf("Failed to find clock node. Check device tree\n");
264 int arch_cpu_init(void)
266 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
268 * ROM might disable clock for SCTR,
269 * enable the clock before timer_init.
271 if (IS_ENABLED(CONFIG_SPL_BUILD))
272 clock_enable(CCGR_SCTR, 1);
274 * Init timer at very early state, because sscg pll setting
279 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
281 imx_set_wdog_powerdown(false);
285 clock_enable(CCGR_OCOTP, 1);
286 if (readl(&ocotp->ctrl) & 0x200)
287 writel(0x200, &ocotp->ctrl_clr);
293 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
294 struct rom_api *g_rom_api = (struct rom_api *)0x980;
296 enum boot_device get_boot_device(void)
298 volatile gd_t *pgd = gd;
303 enum boot_device boot_dev = SD1_BOOT;
305 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
306 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
309 if (ret != ROM_API_OKAY) {
310 puts("ROMAPI: failure at query_boot_info\n");
314 boot_type = boot >> 16;
315 boot_instance = (boot >> 8) & 0xff;
319 boot_dev = boot_instance + SD1_BOOT;
321 case BT_DEV_TYPE_MMC:
322 boot_dev = boot_instance + MMC1_BOOT;
324 case BT_DEV_TYPE_NAND:
325 boot_dev = NAND_BOOT;
327 case BT_DEV_TYPE_FLEXSPINOR:
328 boot_dev = QSPI_BOOT;
330 case BT_DEV_TYPE_USB:
341 bool is_usb_boot(void)
343 return get_boot_device() == USB_BOOT;
346 #ifdef CONFIG_OF_SYSTEM_SETUP
347 int ft_system_setup(void *blob, bd_t *bd)
353 /* Disable the CPU idle for A0 chip since the HW does not support it */
354 if (is_soc_rev(CHIP_REV_1_0)) {
355 static const char * const nodes_path[] = {
362 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
363 nodeoff = fdt_path_offset(blob, nodes_path[i]);
365 continue; /* Not found, skip it */
367 printf("Found %s node\n", nodes_path[i]);
369 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
371 printf("Unable to update property %s:%s, err=%s\n",
372 nodes_path[i], "status", fdt_strerror(rc));
376 printf("Remove %s:%s\n", nodes_path[i],
385 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
386 void reset_cpu(ulong addr)
388 struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
391 wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
393 /* Clear WDA to trigger WDOG_B immediately */
394 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
398 * spin for .5 seconds before reset