arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/mach-imx/hab.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/syscounter.h>
  17 #include <asm/armv8/mmu.h>
  18 #include <dm/uclass.h>
  19 #include <errno.h>
  20 #include <fdt_support.h>
  21 #include <fsl_wdog.h>
  22 #include <imx_sip.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #if defined(CONFIG_IMX_HAB)
  27 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  28         .bank = 1,
  29         .word = 3,
  30 };
  31 #endif
  32
  33 int timer_init(void)
  34 {
  35 #ifdef CONFIG_SPL_BUILD
  36         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  37         unsigned long freq = readl(&sctr->cntfid0);
  38
  39         /* Update with accurate clock frequency */
  40         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  41
  42         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  43                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  44 #endif
  45
  46         gd->arch.tbl = 0;
  47         gd->arch.tbu = 0;
  48
  49         return 0;
  50 }
  51
  52 void enable_tzc380(void)
  53 {
  54         struct iomuxc_gpr_base_regs *gpr =
  55                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  56
  57         /* Enable TZASC and lock setting */
  58         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  59         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  60         if (is_imx8mm() || is_imx8mn())
  61                 setbits_le32(&gpr->gpr[10], BIT(1));
  62         /*
  63          * set Region 0 attribute to allow secure and non-secure
  64          * read/write permission. Found some masters like usb dwc3
  65          * controllers can't work with secure memory.
  66          */
  67         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  68 }
  69
  70 void set_wdog_reset(struct wdog_regs *wdog)
  71 {
  72         /*
  73          * Output WDOG_B signal to reset external pmic or POR_B decided by
  74          * the board design. Without external reset, the peripherals/DDR/
  75          * PMIC are not reset, that may cause system working abnormal.
  76          * WDZST bit is write-once only bit. Align this bit in kernel,
  77          * otherwise kernel code will have no chance to set this bit.
  78          */
  79         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  80 }
  81
  82 static struct mm_region imx8m_mem_map[] = {
  83         {
  84                 /* ROM */
  85                 .virt = 0x0UL,
  86                 .phys = 0x0UL,
  87                 .size = 0x100000UL,
  88                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  89                          PTE_BLOCK_OUTER_SHARE
  90         }, {
  91                 /* CAAM */
  92                 .virt = 0x100000UL,
  93                 .phys = 0x100000UL,
  94                 .size = 0x8000UL,
  95                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  96                          PTE_BLOCK_NON_SHARE |
  97                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  98         }, {
  99                 /* TCM */
 100                 .virt = 0x7C0000UL,
 101                 .phys = 0x7C0000UL,
 102                 .size = 0x80000UL,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 104                          PTE_BLOCK_NON_SHARE |
 105                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 106         }, {
 107                 /* OCRAM */
 108                 .virt = 0x900000UL,
 109                 .phys = 0x900000UL,
 110                 .size = 0x200000UL,
 111                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 112                          PTE_BLOCK_OUTER_SHARE
 113         }, {
 114                 /* AIPS */
 115                 .virt = 0xB00000UL,
 116                 .phys = 0xB00000UL,
 117                 .size = 0x3f500000UL,
 118                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 119                          PTE_BLOCK_NON_SHARE |
 120                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 121         }, {
 122                 /* DRAM1 */
 123                 .virt = 0x40000000UL,
 124                 .phys = 0x40000000UL,
 125                 .size = PHYS_SDRAM_SIZE,
 126                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 127                          PTE_BLOCK_OUTER_SHARE
 128 #ifdef PHYS_SDRAM_2_SIZE
 129         }, {
 130                 /* DRAM2 */
 131                 .virt = 0x100000000UL,
 132                 .phys = 0x100000000UL,
 133                 .size = PHYS_SDRAM_2_SIZE,
 134                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 135                          PTE_BLOCK_OUTER_SHARE
 136 #endif
 137         }, {
 138                 /* List terminator */
 139                 0,
 140         }
 141 };
 142
 143 struct mm_region *mem_map = imx8m_mem_map;
 144
 145 void enable_caches(void)
 146 {
 147         /*
 148          * If OPTEE runs, remove OPTEE memory from MMU table to
 149          * avoid speculative prefetch. OPTEE runs at the top of
 150          * the first memory bank
 151          */
 152         if (rom_pointer[1])
 153                 imx8m_mem_map[5].size -= rom_pointer[1];
 154
 155         icache_enable();
 156         dcache_enable();
 157 }
 158
 159 static u32 get_cpu_variant_type(u32 type)
 160 {
 161         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 162         struct fuse_bank *bank = &ocotp->bank[1];
 163         struct fuse_bank1_regs *fuse =
 164                 (struct fuse_bank1_regs *)bank->fuse_regs;
 165
 166         u32 value = readl(&fuse->tester4);
 167
 168         if (type == MXC_CPU_IMX8MM) {
 169                 switch (value & 0x3) {
 170                 case 2:
 171                         if (value & 0x1c0000)
 172                                 return MXC_CPU_IMX8MMDL;
 173                         else
 174                                 return MXC_CPU_IMX8MMD;
 175                 case 3:
 176                         if (value & 0x1c0000)
 177                                 return MXC_CPU_IMX8MMSL;
 178                         else
 179                                 return MXC_CPU_IMX8MMS;
 180                 default:
 181                         if (value & 0x1c0000)
 182                                 return MXC_CPU_IMX8MML;
 183                         break;
 184                 }
 185         }
 186
 187         return type;
 188 }
 189
 190 u32 get_cpu_rev(void)
 191 {
 192         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 193         u32 reg = readl(&ana_pll->digprog);
 194         u32 type = (reg >> 16) & 0xff;
 195         u32 major_low = (reg >> 8) & 0xff;
 196         u32 rom_version;
 197
 198         reg &= 0xff;
 199
 200         /* i.MX8MM */
 201         if (major_low == 0x42) {
 202                 return (MXC_CPU_IMX8MN << 12) | reg;
 203         } else if (major_low == 0x41) {
 204                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 205         } else {
 206                 if (reg == CHIP_REV_1_0) {
 207                         /*
 208                          * For B0 chip, the DIGPROG is not updated,
 209                          * it is still TO1.0. we have to check ROM
 210                          * version or OCOTP_READ_FUSE_DATA.
 211                          * 0xff0055aa is magic number for B1.
 212                          */
 213                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 214                                 reg = CHIP_REV_2_1;
 215                         } else {
 216                                 rom_version =
 217                                         readl((void __iomem *)ROM_VERSION_A0);
 218                                 if (rom_version != CHIP_REV_1_0) {
 219                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 220                                         if (rom_version == CHIP_REV_2_0)
 221                                                 reg = CHIP_REV_2_0;
 222                                 }
 223                         }
 224                 }
 225         }
 226
 227         return (type << 12) | reg;
 228 }
 229
 230 static void imx_set_wdog_powerdown(bool enable)
 231 {
 232         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 233         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 234         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 235
 236         /* Write to the PDE (Power Down Enable) bit */
 237         writew(enable, &wdog1->wmcr);
 238         writew(enable, &wdog2->wmcr);
 239         writew(enable, &wdog3->wmcr);
 240 }
 241
 242 int arch_cpu_init_dm(void)
 243 {
 244         struct udevice *dev;
 245         int ret;
 246
 247         if (CONFIG_IS_ENABLED(CLK)) {
 248                 ret = uclass_get_device_by_name(UCLASS_CLK,
 249                                                 "clock-controller@30380000",
 250                                                 &dev);
 251                 if (ret < 0) {
 252                         printf("Failed to find clock node. Check device tree\n");
 253                         return ret;
 254                 }
 255         }
 256
 257         return 0;
 258 }
 259
 260 int arch_cpu_init(void)
 261 {
 262         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 263         /*
 264          * ROM might disable clock for SCTR,
 265          * enable the clock before timer_init.
 266          */
 267         if (IS_ENABLED(CONFIG_SPL_BUILD))
 268                 clock_enable(CCGR_SCTR, 1);
 269         /*
 270          * Init timer at very early state, because sscg pll setting
 271          * will use it
 272          */
 273         timer_init();
 274
 275         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 276                 clock_init();
 277                 imx_set_wdog_powerdown(false);
 278         }
 279
 280         if (is_imx8mq()) {
 281                 clock_enable(CCGR_OCOTP, 1);
 282                 if (readl(&ocotp->ctrl) & 0x200)
 283                         writel(0x200, &ocotp->ctrl_clr);
 284         }
 285
 286         return 0;
 287 }
 288
 289 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 290 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 291
 292 enum boot_device get_boot_device(void)
 293 {
 294         volatile gd_t *pgd = gd;
 295         int ret;
 296         u32 boot;
 297         u16 boot_type;
 298         u8 boot_instance;
 299         enum boot_device boot_dev = SD1_BOOT;
 300
 301         ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
 302                                           ((uintptr_t)&boot) ^ QUERY_BT_DEV);
 303         gd = pgd;
 304
 305         if (ret != ROM_API_OKAY) {
 306                 puts("ROMAPI: failure at query_boot_info\n");
 307                 return -1;
 308         }
 309
 310         boot_type = boot >> 16;
 311         boot_instance = (boot >> 8) & 0xff;
 312
 313         switch (boot_type) {
 314         case BT_DEV_TYPE_SD:
 315                 boot_dev = boot_instance + SD1_BOOT;
 316                 break;
 317         case BT_DEV_TYPE_MMC:
 318                 boot_dev = boot_instance + MMC1_BOOT;
 319                 break;
 320         case BT_DEV_TYPE_NAND:
 321                 boot_dev = NAND_BOOT;
 322                 break;
 323         case BT_DEV_TYPE_FLEXSPINOR:
 324                 boot_dev = QSPI_BOOT;
 325                 break;
 326         case BT_DEV_TYPE_USB:
 327                 boot_dev = USB_BOOT;
 328                 break;
 329         default:
 330                 break;
 331         }
 332
 333         return boot_dev;
 334 }
 335 #endif
 336
 337 bool is_usb_boot(void)
 338 {
 339         return get_boot_device() == USB_BOOT;
 340 }
 341
 342 #ifdef CONFIG_OF_SYSTEM_SETUP
 343 int ft_system_setup(void *blob, bd_t *bd)
 344 {
 345         int i = 0;
 346         int rc;
 347         int nodeoff;
 348
 349         /* Disable the CPU idle for A0 chip since the HW does not support it */
 350         if (is_soc_rev(CHIP_REV_1_0)) {
 351                 static const char * const nodes_path[] = {
 352                         "/cpus/cpu@0",
 353                         "/cpus/cpu@1",
 354                         "/cpus/cpu@2",
 355                         "/cpus/cpu@3",
 356                 };
 357
 358                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 359                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 360                         if (nodeoff < 0)
 361                                 continue; /* Not found, skip it */
 362
 363                         printf("Found %s node\n", nodes_path[i]);
 364
 365                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 366                         if (rc) {
 367                                 printf("Unable to update property %s:%s, err=%s\n",
 368                                        nodes_path[i], "status", fdt_strerror(rc));
 369                                 return rc;
 370                         }
 371
 372                         printf("Remove %s:%s\n", nodes_path[i],
 373                                "cpu-idle-states");
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379 #endif
 380
 381 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
 382 void reset_cpu(ulong addr)
 383 {
 384        struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
 385
 386        if (!addr)
 387                wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 388
 389        /* Clear WDA to trigger WDOG_B immediately */
 390        writew((WCR_WDE | WCR_SRS), &wdog->wcr);
 391
 392        while (1) {
 393                /*
 394                 * spin for .5 seconds before reset
 395                 */
 396        }
 397 }
 398 #endif