1 // SPDX-License-Identifier: GPL-2.0+
5 * Peng Fan <peng.fan@nxp.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/sys_proto.h>
14 #include <linux/iopoll.h>
16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
18 static u32 decode_frac_pll(enum clk_root_src frac_pll)
20 u32 pll_cfg0, pll_cfg1, pllout;
21 u32 pll_refclk_sel, pll_refclk;
22 u32 divr_val, divq_val, divf_val, divff, divfi;
23 u32 pllout_div_shift, pllout_div_mask, pllout_div;
27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
29 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
30 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
33 printf("Frac PLL %d not supporte\n", frac_pll);
37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
38 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
41 if (pll_cfg0 & FRAC_PLL_PD_MASK)
44 /* output not enabled */
45 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
48 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
50 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
51 pll_refclk = 25000000u;
52 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
53 pll_refclk = 27000000u;
54 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
55 pll_refclk = 27000000u;
59 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
62 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
63 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
64 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
66 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
67 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
68 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
70 divf_val = 1 + divfi + divff / (1 << 24);
72 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
75 return pllout / (pllout_div + 1);
78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
80 u32 pll_cfg0, pll_cfg1, pll_cfg2;
81 u32 pll_refclk_sel, pll_refclk;
82 u32 divr1, divr2, divf1, divf2, divq, div;
85 u32 pllout_div_shift, pllout_div_mask, pllout_div;
89 case SYSTEM_PLL1_800M_CLK:
90 case SYSTEM_PLL1_400M_CLK:
91 case SYSTEM_PLL1_266M_CLK:
92 case SYSTEM_PLL1_200M_CLK:
93 case SYSTEM_PLL1_160M_CLK:
94 case SYSTEM_PLL1_133M_CLK:
95 case SYSTEM_PLL1_100M_CLK:
96 case SYSTEM_PLL1_80M_CLK:
97 case SYSTEM_PLL1_40M_CLK:
98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
101 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
102 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
104 case SYSTEM_PLL2_1000M_CLK:
105 case SYSTEM_PLL2_500M_CLK:
106 case SYSTEM_PLL2_333M_CLK:
107 case SYSTEM_PLL2_250M_CLK:
108 case SYSTEM_PLL2_200M_CLK:
109 case SYSTEM_PLL2_166M_CLK:
110 case SYSTEM_PLL2_125M_CLK:
111 case SYSTEM_PLL2_100M_CLK:
112 case SYSTEM_PLL2_50M_CLK:
113 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
114 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
115 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
116 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
117 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
119 case SYSTEM_PLL3_CLK:
120 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
121 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
122 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
123 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
124 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
127 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
128 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
129 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
130 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
131 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
134 printf("sscg pll %d not supporte\n", sscg_pll);
140 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
143 case SYSTEM_PLL3_CLK:
144 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
147 case SYSTEM_PLL2_1000M_CLK:
148 case SYSTEM_PLL1_800M_CLK:
149 pll_clke = SSCG_PLL_CLKE_MASK;
152 case SYSTEM_PLL2_500M_CLK:
153 case SYSTEM_PLL1_400M_CLK:
154 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
157 case SYSTEM_PLL2_333M_CLK:
158 case SYSTEM_PLL1_266M_CLK:
159 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
162 case SYSTEM_PLL2_250M_CLK:
163 case SYSTEM_PLL1_200M_CLK:
164 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
167 case SYSTEM_PLL2_200M_CLK:
168 case SYSTEM_PLL1_160M_CLK:
169 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
172 case SYSTEM_PLL2_166M_CLK:
173 case SYSTEM_PLL1_133M_CLK:
174 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
177 case SYSTEM_PLL2_125M_CLK:
178 case SYSTEM_PLL1_100M_CLK:
179 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
182 case SYSTEM_PLL2_100M_CLK:
183 case SYSTEM_PLL1_80M_CLK:
184 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
187 case SYSTEM_PLL2_50M_CLK:
188 case SYSTEM_PLL1_40M_CLK:
189 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
193 printf("sscg pll %d not supporte\n", sscg_pll);
198 if (pll_cfg0 & SSCG_PLL_PD_MASK)
201 /* output not enabled */
202 if ((pll_cfg0 & pll_clke) == 0)
205 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
206 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
208 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
210 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
211 pll_refclk = 25000000u;
212 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
213 pll_refclk = 27000000u;
214 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
215 pll_refclk = 27000000u;
219 /* We assume bypass1/2 are the same value */
220 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
221 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
225 SSCG_PLL_REF_DIVR1_SHIFT;
226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
227 SSCG_PLL_REF_DIVR2_SHIFT;
228 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
229 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
230 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
231 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
232 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
233 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
242 (divr2 + 1) * (divf2 + 1) / (divq + 1);
244 return pllout / (pllout_div + 1) / div;
247 static u32 get_root_src_clk(enum clk_root_src root_src)
257 return decode_frac_pll(root_src);
258 case SYSTEM_PLL1_800M_CLK:
259 case SYSTEM_PLL1_400M_CLK:
260 case SYSTEM_PLL1_266M_CLK:
261 case SYSTEM_PLL1_200M_CLK:
262 case SYSTEM_PLL1_160M_CLK:
263 case SYSTEM_PLL1_133M_CLK:
264 case SYSTEM_PLL1_100M_CLK:
265 case SYSTEM_PLL1_80M_CLK:
266 case SYSTEM_PLL1_40M_CLK:
267 case SYSTEM_PLL2_1000M_CLK:
268 case SYSTEM_PLL2_500M_CLK:
269 case SYSTEM_PLL2_333M_CLK:
270 case SYSTEM_PLL2_250M_CLK:
271 case SYSTEM_PLL2_200M_CLK:
272 case SYSTEM_PLL2_166M_CLK:
273 case SYSTEM_PLL2_125M_CLK:
274 case SYSTEM_PLL2_100M_CLK:
275 case SYSTEM_PLL2_50M_CLK:
276 case SYSTEM_PLL3_CLK:
277 return decode_sscg_pll(root_src);
285 static u32 get_root_clk(enum clk_root_index clock_id)
287 enum clk_root_src root_src;
288 u32 post_podf, pre_podf, root_src_clk;
290 if (clock_root_enabled(clock_id) <= 0)
293 if (clock_get_prediv(clock_id, &pre_podf) < 0)
296 if (clock_get_postdiv(clock_id, &post_podf) < 0)
299 if (clock_get_src(clock_id, &root_src) < 0)
302 root_src_clk = get_root_src_clk(root_src);
304 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
307 #ifdef CONFIG_MXC_OCOTP
308 void enable_ocotp_clk(unsigned char enable)
310 clock_enable(CCGR_OCOTP, !!enable);
314 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
316 /* 0 - 3 is valid i2c num */
320 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
325 unsigned int mxc_get_clock(enum mxc_clock clk)
331 return get_root_clk(ARM_A53_CLK_ROOT);
333 clock_get_target_val(IPG_CLK_ROOT, &val);
335 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
337 return get_root_clk(USDHC1_CLK_ROOT);
339 return get_root_clk(USDHC2_CLK_ROOT);
341 return get_root_clk(clk);
345 u32 imx_get_uartclk(void)
347 return mxc_get_clock(UART1_CLK_ROOT);
350 void mxs_set_lcdclk(u32 base_addr, u32 freq)
353 * LCDIF_PIXEL_CLK: select 800MHz root clock,
354 * select pre divider 8, output is 100 MHz
356 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
357 CLK_ROOT_SOURCE_SEL(4) |
358 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
361 void init_wdog_clk(void)
363 clock_enable(CCGR_WDOG1, 0);
364 clock_enable(CCGR_WDOG2, 0);
365 clock_enable(CCGR_WDOG3, 0);
366 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
367 CLK_ROOT_SOURCE_SEL(0));
368 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
369 CLK_ROOT_SOURCE_SEL(0));
370 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
371 CLK_ROOT_SOURCE_SEL(0));
372 clock_enable(CCGR_WDOG1, 1);
373 clock_enable(CCGR_WDOG2, 1);
374 clock_enable(CCGR_WDOG3, 1);
378 void init_nand_clk(void)
380 clock_enable(CCGR_RAWNAND, 0);
381 clock_set_target_val(NAND_CLK_ROOT,
382 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
383 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
384 clock_enable(CCGR_RAWNAND, 1);
387 void init_uart_clk(u32 index)
389 /* Set uart clock root 25M OSC */
392 clock_enable(CCGR_UART1, 0);
393 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
394 CLK_ROOT_SOURCE_SEL(0));
395 clock_enable(CCGR_UART1, 1);
398 clock_enable(CCGR_UART2, 0);
399 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
400 CLK_ROOT_SOURCE_SEL(0));
401 clock_enable(CCGR_UART2, 1);
404 clock_enable(CCGR_UART3, 0);
405 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
406 CLK_ROOT_SOURCE_SEL(0));
407 clock_enable(CCGR_UART3, 1);
410 clock_enable(CCGR_UART4, 0);
411 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
412 CLK_ROOT_SOURCE_SEL(0));
413 clock_enable(CCGR_UART4, 1);
416 printf("Invalid uart index\n");
421 void init_clk_usdhc(u32 index)
424 * set usdhc clock root
429 clock_enable(CCGR_USDHC1, 0);
430 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
431 CLK_ROOT_SOURCE_SEL(1) |
432 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
433 clock_enable(CCGR_USDHC1, 1);
436 clock_enable(CCGR_USDHC2, 0);
437 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
438 CLK_ROOT_SOURCE_SEL(1) |
439 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
440 clock_enable(CCGR_USDHC2, 1);
443 printf("Invalid usdhc index\n");
448 int set_clk_qspi(void)
454 clock_enable(CCGR_QSPI, 0);
455 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
456 CLK_ROOT_SOURCE_SEL(7));
457 clock_enable(CCGR_QSPI, 1);
462 #ifdef CONFIG_FEC_MXC
463 int set_clk_enet(enum enet_freq type)
470 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
473 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
476 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
482 /* disable the clock first */
483 clock_enable(CCGR_ENET1, 0);
484 clock_enable(CCGR_SIM_ENET, 0);
486 /* set enet axi clock 266Mhz */
487 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
488 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
489 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
490 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
492 target = CLK_ROOT_ON | enet1_ref |
493 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
494 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
495 clock_set_target_val(ENET_REF_CLK_ROOT, target);
497 target = CLK_ROOT_ON |
498 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
499 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
500 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
501 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
504 clock_enable(CCGR_SIM_ENET, 1);
505 clock_enable(CCGR_ENET1, 1);
511 u32 imx_get_fecclk(void)
513 return get_root_clk(ENET_AXI_CLK_ROOT);
516 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
517 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
519 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
521 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
525 void dram_enable_bypass(ulong clk_val)
528 struct dram_bypass_clk_setting *config;
530 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
531 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
535 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
536 printf("No matched freq table %lu\n", clk_val);
540 config = &imx8mq_dram_bypass_tbl[i];
542 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
543 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
544 CLK_ROOT_PRE_DIV(config->alt_pre_div));
545 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
546 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
547 CLK_ROOT_PRE_DIV(config->apb_pre_div));
548 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
549 CLK_ROOT_SOURCE_SEL(1));
552 void dram_disable_bypass(void)
554 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
555 CLK_ROOT_SOURCE_SEL(0));
556 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
557 CLK_ROOT_SOURCE_SEL(4) |
558 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
561 #ifdef CONFIG_SPL_BUILD
562 void dram_pll_init(ulong pll_val)
565 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
566 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
569 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
570 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
574 val = readl(pll_cfg_reg2);
575 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
576 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
577 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
578 SSCG_PLL_REF_DIVR2_MASK);
579 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
580 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
581 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
582 val |= SSCG_PLL_REF_DIVR2_VAL(29);
583 writel(val, pll_cfg_reg2);
586 val = readl(pll_cfg_reg2);
587 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
588 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
589 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
590 SSCG_PLL_REF_DIVR2_MASK);
591 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
592 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
593 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
594 val |= SSCG_PLL_REF_DIVR2_VAL(29);
595 writel(val, pll_cfg_reg2);
598 val = readl(pll_cfg_reg2);
599 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
600 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
601 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
602 SSCG_PLL_REF_DIVR2_MASK);
603 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
604 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
605 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
606 val |= SSCG_PLL_REF_DIVR2_VAL(29);
607 writel(val, pll_cfg_reg2);
610 val = readl(pll_cfg_reg2);
611 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
612 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
613 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
614 SSCG_PLL_REF_DIVR2_MASK);
615 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
616 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
617 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
618 val |= SSCG_PLL_REF_DIVR2_VAL(30);
619 writel(val, pll_cfg_reg2);
625 /* Clear power down bit */
626 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
627 /* Eanble ARM_PLL/SYS_PLL */
628 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
631 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
633 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
635 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
639 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
641 void __iomem *pll_cfg0, __iomem *pll_cfg1;
642 u32 val_cfg0, val_cfg1;
647 pll_cfg0 = &ana_pll->arm_pll_cfg0;
648 pll_cfg1 = &ana_pll->arm_pll_cfg1;
650 if (val == FRAC_PLL_OUT_1000M)
651 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
653 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
654 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
655 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
656 FRAC_PLL_REFCLK_DIV_VAL(4) |
657 FRAC_PLL_OUTPUT_DIV_VAL(0);
663 /* bypass the clock */
664 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
666 writel(val_cfg1, pll_cfg1);
667 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
668 val_cfg0 = readl(pll_cfg0);
669 /* unbypass the clock */
670 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
671 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
672 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
674 printf("%s timeout\n", __func__);
675 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
685 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
686 CLK_ROOT_SOURCE_SEL(0));
689 * 8MQ only supports two grades: consumer and industrial.
690 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
692 grade = get_cpu_temp_grade(NULL, NULL);
694 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
695 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
696 CLK_ROOT_SOURCE_SEL(1) |
697 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
699 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
700 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
701 CLK_ROOT_SOURCE_SEL(1) |
702 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
705 * According to ANAMIX SPEC
706 * sys pll1 fixed at 800MHz
707 * sys pll2 fixed at 1GHz
708 * Here we only enable the outputs.
710 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
711 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
712 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
713 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
714 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
716 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
717 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
718 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
719 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
720 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
722 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
723 CLK_ROOT_SOURCE_SEL(1));
726 clock_enable(CCGR_TSENSOR, 1);
727 clock_enable(CCGR_OCOTP, 1);
729 /* config GIC ROOT to sys_pll2_200m */
730 clock_enable(CCGR_GIC, 0);
731 clock_set_target_val(GIC_CLK_ROOT,
732 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
733 clock_enable(CCGR_GIC, 1);
742 #ifndef CONFIG_SPL_BUILD
743 static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
748 freq = decode_frac_pll(ARM_PLL_CLK);
749 printf("ARM_PLL %8d MHz\n", freq / 1000000);
750 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
751 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
752 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
753 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
754 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
755 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
756 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
757 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
758 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
759 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
760 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
761 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
762 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
763 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
764 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
765 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
766 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
767 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
768 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
769 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
770 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
771 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
772 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
773 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
774 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
775 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
776 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
777 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
778 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
779 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
780 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
781 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
782 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
783 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
784 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
785 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
786 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
787 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
788 freq = mxc_get_clock(UART1_CLK_ROOT);
789 printf("UART1 %8d MHz\n", freq / 1000000);
790 freq = mxc_get_clock(USDHC1_CLK_ROOT);
791 printf("USDHC1 %8d MHz\n", freq / 1000000);
792 freq = mxc_get_clock(QSPI_CLK_ROOT);
793 printf("QSPI %8d MHz\n", freq / 1000000);
798 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,