1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018, 2021 NXP
14 #include <asm/cache.h>
15 #include <asm/global_data.h>
16 #include <dm/device-internal.h>
18 #include <dm/uclass.h>
22 #include <firmware/imx/sci/sci.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch-imx/cpu.h>
25 #include <asm/armv8/cpu.h>
26 #include <asm/armv8/mmu.h>
27 #include <asm/setup.h>
28 #include <asm/mach-imx/boot_mode.h>
29 #include <power-domain.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define BT_PASSOVER_TAG 0x504F
36 struct pass_over_info_t *get_pass_over_info(void)
38 struct pass_over_info_t *p =
39 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
41 if (p->barker != BT_PASSOVER_TAG ||
42 p->len != sizeof(struct pass_over_info_t))
48 int arch_cpu_init(void)
50 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
51 spl_save_restore_data();
54 #ifdef CONFIG_SPL_BUILD
55 struct pass_over_info_t *pass_over;
57 if (is_soc_rev(CHIP_REV_A)) {
58 pass_over = get_pass_over_info();
59 if (pass_over && pass_over->g_ap_mu == 0) {
61 * When ap_mu is 0, means the U-Boot booted
62 * from first container
64 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
72 static int imx8_init_mu(void *ctx, struct event *event)
77 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
79 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
81 printf("could not get scu %d\n", ret);
86 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
94 EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
96 #if defined(CONFIG_ARCH_MISC_INIT)
97 int arch_misc_init(void)
99 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
103 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
105 printf("Failed to initialize caam_jr: %d\n", ret);
112 #ifdef CONFIG_IMX_BOOTAUX
115 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
117 sc_rsrc_t core_rsrc, mu_rsrc;
118 sc_faddr_t tcml_addr;
119 u32 tcml_size = SZ_128K;
124 core_rsrc = SC_R_M4_0_PID0;
125 tcml_addr = 0x34FE0000;
126 mu_rsrc = SC_R_M4_0_MU_1A;
129 core_rsrc = SC_R_M4_1_PID0;
130 tcml_addr = 0x38FE0000;
131 mu_rsrc = SC_R_M4_1_MU_1A;
134 printf("Not support this core boot up, ID:%u\n", core_id);
138 addr = (sc_faddr_t)boot_private_data;
140 if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
141 printf("Wrong image address 0x%lx, should not in TCML\n",
146 printf("Power on M4 and MU\n");
148 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
151 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
154 printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
156 if (addr != tcml_addr)
157 memcpy((void *)tcml_addr, (void *)addr, tcml_size);
159 printf("Start M4 %u\n", core_id);
160 if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
163 printf("bootaux complete\n");
168 #ifdef CONFIG_IMX8QXP
169 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
171 sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE;
172 sc_faddr_t aux_core_ram;
178 core_rsrc = SC_R_M4_0_PID0;
179 aux_core_ram = 0x34FE0000;
180 mu_rsrc = SC_R_M4_0_MU_1A;
184 core_rsrc = SC_R_DSP;
185 aux_core_ram = 0x596f8000;
189 printf("Not support this core boot up, ID:%u\n", core_id);
193 addr = (sc_faddr_t)boot_private_data;
195 if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
196 printf("Wrong image address 0x%lx, should not in aux core ram\n",
201 printf("Power on aux core %d\n", core_id);
203 if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
206 if (mu_rsrc != SC_R_NONE) {
207 if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
212 struct power_domain pd;
214 if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
215 printf("Error enable clock\n");
219 if (!power_domain_lookup_name("audio_sai0", &pd)) {
220 if (power_domain_on(&pd)) {
221 printf("Error power on SAI0\n");
226 if (!power_domain_lookup_name("audio_ocram", &pd)) {
227 if (power_domain_on(&pd)) {
228 printf("Error power on HIFI RAM\n");
234 printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
236 /* M4 use bin file */
237 memcpy((void *)aux_core_ram, (void *)addr, size);
239 /* HIFI use elf file */
240 if (!valid_elf_image(addr))
242 addr = load_elf_image_shdr(addr);
245 printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
247 if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
250 printf("bootaux complete\n");
255 int arch_auxiliary_core_check_up(u32 core_id)
258 sc_pm_power_mode_t power_mode;
262 core_rsrc = SC_R_M4_0_PID0;
266 core_rsrc = SC_R_M4_1_PID0;
270 printf("Not support this core, ID:%u\n", core_id);
274 if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
277 if (power_mode != SC_PM_PW_MODE_OFF)
284 int print_bootinfo(void)
286 enum boot_device bt_dev = get_boot_device();
321 printf("Unknown device %u\n", bt_dev);
328 enum boot_device get_boot_device(void)
330 enum boot_device boot_dev = SD1_BOOT;
334 sc_misc_get_boot_dev(-1, &dev_rsrc);
338 boot_dev = MMC1_BOOT;
347 boot_dev = NAND_BOOT;
350 boot_dev = FLEXSPI_BOOT;
353 boot_dev = SATA_BOOT;
367 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
368 #define FUSE_UNIQUE_ID_WORD0 16
369 #define FUSE_UNIQUE_ID_WORD1 17
370 void get_board_serial(struct tag_serialnr *serialnr)
373 u32 val1 = 0, val2 = 0;
379 word1 = FUSE_UNIQUE_ID_WORD0;
380 word2 = FUSE_UNIQUE_ID_WORD1;
382 err = sc_misc_otp_fuse_read(-1, word1, &val1);
384 printf("%s fuse %d read error: %d\n", __func__, word1, err);
388 err = sc_misc_otp_fuse_read(-1, word2, &val2);
390 printf("%s fuse %d read error: %d\n", __func__, word2, err);
393 serialnr->low = val1;
394 serialnr->high = val2;
396 #endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/
398 #ifdef CONFIG_ENV_IS_IN_MMC
399 __weak int board_mmc_get_env_dev(int devno)
401 return CONFIG_SYS_MMC_ENV_DEV;
404 int mmc_get_env_dev(void)
409 sc_misc_get_boot_dev(-1, &dev_rsrc);
422 /* If not boot from sd/mmc, use default value */
423 return CONFIG_SYS_MMC_ENV_DEV;
426 return board_mmc_get_env_dev(devno);
430 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
432 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
433 sc_faddr_t *addr_end)
435 sc_faddr_t start, end;
439 owned = sc_rm_is_memreg_owned(-1, mr);
441 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
443 printf("Memreg get info failed, %d\n", ret);
446 debug("0x%llx -- 0x%llx\n", start, end);
456 __weak void board_mem_get_layout(u64 *phys_sdram_1_start,
457 u64 *phys_sdram_1_size,
458 u64 *phys_sdram_2_start,
459 u64 *phys_sdram_2_size)
461 *phys_sdram_1_start = PHYS_SDRAM_1;
462 *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
463 *phys_sdram_2_start = PHYS_SDRAM_2;
464 *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
467 phys_size_t get_effective_memsize(void)
470 sc_faddr_t start, end, end1, start_aligned;
471 u64 phys_sdram_1_start, phys_sdram_1_size;
472 u64 phys_sdram_2_start, phys_sdram_2_size;
475 board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
476 &phys_sdram_2_start, &phys_sdram_2_size);
479 end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
480 for (mr = 0; mr < 64; mr++) {
481 err = get_owned_memreg(mr, &start, &end);
483 start_aligned = roundup(start, MEMSTART_ALIGNMENT);
484 /* Too small memory region, not use it */
485 if (start_aligned > end)
488 /* Find the memory region runs the U-Boot */
489 if (start >= phys_sdram_1_start && start <= end1 &&
490 (start <= CONFIG_TEXT_BASE &&
491 end >= CONFIG_TEXT_BASE)) {
493 ((sc_faddr_t)phys_sdram_1_start +
495 return (end - phys_sdram_1_start + 1);
497 return phys_sdram_1_size;
502 return phys_sdram_1_size;
508 sc_faddr_t start, end, end1, end2;
509 u64 phys_sdram_1_start, phys_sdram_1_size;
510 u64 phys_sdram_2_start, phys_sdram_2_size;
513 board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
514 &phys_sdram_2_start, &phys_sdram_2_size);
516 end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
517 end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
518 for (mr = 0; mr < 64; mr++) {
519 err = get_owned_memreg(mr, &start, &end);
521 start = roundup(start, MEMSTART_ALIGNMENT);
522 /* Too small memory region, not use it */
526 if (start >= phys_sdram_1_start && start <= end1) {
527 if ((end + 1) <= end1)
528 gd->ram_size += end - start + 1;
530 gd->ram_size += end1 - start;
531 } else if (start >= phys_sdram_2_start &&
533 if ((end + 1) <= end2)
534 gd->ram_size += end - start + 1;
536 gd->ram_size += end2 - start;
541 /* If error, set to the default value */
543 gd->ram_size = phys_sdram_1_size;
544 gd->ram_size += phys_sdram_2_size;
549 static void dram_bank_sort(int current_bank)
554 while (current_bank > 0) {
555 if (gd->bd->bi_dram[current_bank - 1].start >
556 gd->bd->bi_dram[current_bank].start) {
557 start = gd->bd->bi_dram[current_bank - 1].start;
558 size = gd->bd->bi_dram[current_bank - 1].size;
560 gd->bd->bi_dram[current_bank - 1].start =
561 gd->bd->bi_dram[current_bank].start;
562 gd->bd->bi_dram[current_bank - 1].size =
563 gd->bd->bi_dram[current_bank].size;
565 gd->bd->bi_dram[current_bank].start = start;
566 gd->bd->bi_dram[current_bank].size = size;
572 int dram_init_banksize(void)
575 sc_faddr_t start, end, end1, end2;
577 u64 phys_sdram_1_start, phys_sdram_1_size;
578 u64 phys_sdram_2_start, phys_sdram_2_size;
581 board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
582 &phys_sdram_2_start, &phys_sdram_2_size);
584 end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
585 end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
586 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
587 err = get_owned_memreg(mr, &start, &end);
589 start = roundup(start, MEMSTART_ALIGNMENT);
590 if (start > end) /* Small memory region, no use it */
593 if (start >= phys_sdram_1_start && start <= end1) {
594 gd->bd->bi_dram[i].start = start;
596 if ((end + 1) <= end1)
597 gd->bd->bi_dram[i].size =
600 gd->bd->bi_dram[i].size = end1 - start;
604 } else if (start >= phys_sdram_2_start && start <= end2) {
605 gd->bd->bi_dram[i].start = start;
607 if ((end + 1) <= end2)
608 gd->bd->bi_dram[i].size =
611 gd->bd->bi_dram[i].size = end2 - start;
619 /* If error, set to the default value */
621 gd->bd->bi_dram[0].start = phys_sdram_1_start;
622 gd->bd->bi_dram[0].size = phys_sdram_1_size;
623 gd->bd->bi_dram[1].start = phys_sdram_2_start;
624 gd->bd->bi_dram[1].size = phys_sdram_2_size;
630 static u64 get_block_attrs(sc_faddr_t addr_start)
632 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
633 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
634 u64 phys_sdram_1_start, phys_sdram_1_size;
635 u64 phys_sdram_2_start, phys_sdram_2_size;
637 board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
638 &phys_sdram_2_start, &phys_sdram_2_size);
640 if ((addr_start >= phys_sdram_1_start &&
641 addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
642 (addr_start >= phys_sdram_2_start &&
643 addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
644 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
649 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
651 sc_faddr_t end1, end2;
652 u64 phys_sdram_1_start, phys_sdram_1_size;
653 u64 phys_sdram_2_start, phys_sdram_2_size;
655 board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
656 &phys_sdram_2_start, &phys_sdram_2_size);
659 end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
660 end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
662 if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
663 if ((addr_end + 1) > end1)
664 return end1 - addr_start;
665 } else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
666 if ((addr_end + 1) > end2)
667 return end2 - addr_start;
670 return (addr_end - addr_start + 1);
673 #define MAX_PTE_ENTRIES 512
674 #define MAX_MEM_MAP_REGIONS 16
676 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
677 struct mm_region *mem_map = imx8_mem_map;
679 void enable_caches(void)
682 sc_faddr_t start, end;
685 /* Create map for registers access from 0x1c000000 to 0x80000000*/
686 imx8_mem_map[0].virt = 0x1c000000UL;
687 imx8_mem_map[0].phys = 0x1c000000UL;
688 imx8_mem_map[0].size = 0x64000000UL;
689 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
690 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
693 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
694 err = get_owned_memreg(mr, &start, &end);
696 imx8_mem_map[i].virt = start;
697 imx8_mem_map[i].phys = start;
698 imx8_mem_map[i].size = get_block_size(start, end);
699 imx8_mem_map[i].attrs = get_block_attrs(start);
704 if (i < MAX_MEM_MAP_REGIONS) {
705 imx8_mem_map[i].size = 0;
706 imx8_mem_map[i].attrs = 0;
708 puts("Error, need more MEM MAP REGIONS reserved\n");
713 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
714 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
715 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
716 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
723 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
724 u64 get_page_table_size(void)
726 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
730 * For each memory region, the max table size:
731 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
733 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
736 * We need to duplicate our page table once to have an emergency pt to
737 * resort to when splitting page tables later on
742 * We may need to split page tables later on if dcache settings change,
743 * so reserve up to 4 (random pick) page tables for that.
751 #if defined(CONFIG_IMX8QM)
752 #define FUSE_MAC0_WORD0 452
753 #define FUSE_MAC0_WORD1 453
754 #define FUSE_MAC1_WORD0 454
755 #define FUSE_MAC1_WORD1 455
756 #elif defined(CONFIG_IMX8QXP)
757 #define FUSE_MAC0_WORD0 708
758 #define FUSE_MAC0_WORD1 709
759 #define FUSE_MAC1_WORD0 710
760 #define FUSE_MAC1_WORD1 711
763 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
765 u32 word[2], val[2] = {};
769 word[0] = FUSE_MAC0_WORD0;
770 word[1] = FUSE_MAC0_WORD1;
772 word[0] = FUSE_MAC1_WORD0;
773 word[1] = FUSE_MAC1_WORD1;
776 for (i = 0; i < 2; i++) {
777 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
783 mac[1] = val[0] >> 8;
784 mac[2] = val[0] >> 16;
785 mac[3] = val[0] >> 24;
787 mac[5] = val[1] >> 8;
789 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
790 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
793 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
796 u32 get_cpu_rev(void)
801 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
805 rev = (id >> 5) & 0xf;
806 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
808 return (id << 12) | rev;
811 void board_boot_order(u32 *spl_boot_list)
813 spl_boot_list[0] = spl_boot_device();
815 if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
816 /* Check whether we own the flexspi0, if not, use NOR boot */
817 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
818 spl_boot_list[0] = BOOT_DEVICE_NOR;
822 bool m4_parts_booted(void)
824 sc_rm_pt_t m4_parts[2];
827 err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
829 printf("%s get resource [%d] owner error: %d\n", __func__,
830 SC_R_M4_0_PID0, err);
834 if (sc_pm_is_partition_started(-1, m4_parts[0]))
838 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
840 printf("%s get resource [%d] owner error: %d\n",
841 __func__, SC_R_M4_1_PID0, err);
845 if (sc_pm_is_partition_started(-1, m4_parts[1]))