1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device-internal.h>
14 #include <dm/uclass.h>
18 #include <asm/arch/sci/sci.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch-imx/cpu.h>
21 #include <asm/armv8/cpu.h>
22 #include <asm/armv8/mmu.h>
23 #include <asm/setup.h>
24 #include <asm/mach-imx/boot_mode.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define BT_PASSOVER_TAG 0x504F
29 struct pass_over_info_t *get_pass_over_info(void)
31 struct pass_over_info_t *p =
32 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
34 if (p->barker != BT_PASSOVER_TAG ||
35 p->len != sizeof(struct pass_over_info_t))
41 int arch_cpu_init(void)
43 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
44 spl_save_restore_data();
47 #ifdef CONFIG_SPL_BUILD
48 struct pass_over_info_t *pass_over;
50 if (is_soc_rev(CHIP_REV_A)) {
51 pass_over = get_pass_over_info();
52 if (pass_over && pass_over->g_ap_mu == 0) {
54 * When ap_mu is 0, means the U-Boot booted
55 * from first container
57 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
65 int arch_cpu_init_dm(void)
70 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
72 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
74 printf("could not get scu %d\n", ret);
79 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
88 int print_bootinfo(void)
90 enum boot_device bt_dev = get_boot_device();
125 printf("Unknown device %u\n", bt_dev);
132 enum boot_device get_boot_device(void)
134 enum boot_device boot_dev = SD1_BOOT;
138 sc_misc_get_boot_dev(-1, &dev_rsrc);
142 boot_dev = MMC1_BOOT;
151 boot_dev = NAND_BOOT;
154 boot_dev = FLEXSPI_BOOT;
157 boot_dev = SATA_BOOT;
171 #ifdef CONFIG_SERIAL_TAG
172 #define FUSE_UNIQUE_ID_WORD0 16
173 #define FUSE_UNIQUE_ID_WORD1 17
174 void get_board_serial(struct tag_serialnr *serialnr)
177 u32 val1 = 0, val2 = 0;
183 word1 = FUSE_UNIQUE_ID_WORD0;
184 word2 = FUSE_UNIQUE_ID_WORD1;
186 err = sc_misc_otp_fuse_read(-1, word1, &val1);
187 if (err != SC_ERR_NONE) {
188 printf("%s fuse %d read error: %d\n", __func__, word1, err);
192 err = sc_misc_otp_fuse_read(-1, word2, &val2);
193 if (err != SC_ERR_NONE) {
194 printf("%s fuse %d read error: %d\n", __func__, word2, err);
197 serialnr->low = val1;
198 serialnr->high = val2;
200 #endif /*CONFIG_SERIAL_TAG*/
202 #ifdef CONFIG_ENV_IS_IN_MMC
203 __weak int board_mmc_get_env_dev(int devno)
205 return CONFIG_SYS_MMC_ENV_DEV;
208 int mmc_get_env_dev(void)
213 sc_misc_get_boot_dev(-1, &dev_rsrc);
226 /* If not boot from sd/mmc, use default value */
227 return CONFIG_SYS_MMC_ENV_DEV;
230 return board_mmc_get_env_dev(devno);
234 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
236 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
237 sc_faddr_t *addr_end)
239 sc_faddr_t start, end;
243 owned = sc_rm_is_memreg_owned(-1, mr);
245 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
247 printf("Memreg get info failed, %d\n", ret);
250 debug("0x%llx -- 0x%llx\n", start, end);
260 phys_size_t get_effective_memsize(void)
263 sc_faddr_t start, end, end1, start_aligned;
266 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
268 for (mr = 0; mr < 64; mr++) {
269 err = get_owned_memreg(mr, &start, &end);
271 start_aligned = roundup(start, MEMSTART_ALIGNMENT);
272 /* Too small memory region, not use it */
273 if (start_aligned > end)
276 /* Find the memory region runs the U-Boot */
277 if (start >= PHYS_SDRAM_1 && start <= end1 &&
278 (start <= CONFIG_SYS_TEXT_BASE &&
279 end >= CONFIG_SYS_TEXT_BASE)) {
280 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
282 return (end - PHYS_SDRAM_1 + 1);
284 return PHYS_SDRAM_1_SIZE;
289 return PHYS_SDRAM_1_SIZE;
295 sc_faddr_t start, end, end1, end2;
298 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
299 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
300 for (mr = 0; mr < 64; mr++) {
301 err = get_owned_memreg(mr, &start, &end);
303 start = roundup(start, MEMSTART_ALIGNMENT);
304 /* Too small memory region, not use it */
308 if (start >= PHYS_SDRAM_1 && start <= end1) {
309 if ((end + 1) <= end1)
310 gd->ram_size += end - start + 1;
312 gd->ram_size += end1 - start;
313 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
314 if ((end + 1) <= end2)
315 gd->ram_size += end - start + 1;
317 gd->ram_size += end2 - start;
322 /* If error, set to the default value */
324 gd->ram_size = PHYS_SDRAM_1_SIZE;
325 gd->ram_size += PHYS_SDRAM_2_SIZE;
330 static void dram_bank_sort(int current_bank)
335 while (current_bank > 0) {
336 if (gd->bd->bi_dram[current_bank - 1].start >
337 gd->bd->bi_dram[current_bank].start) {
338 start = gd->bd->bi_dram[current_bank - 1].start;
339 size = gd->bd->bi_dram[current_bank - 1].size;
341 gd->bd->bi_dram[current_bank - 1].start =
342 gd->bd->bi_dram[current_bank].start;
343 gd->bd->bi_dram[current_bank - 1].size =
344 gd->bd->bi_dram[current_bank].size;
346 gd->bd->bi_dram[current_bank].start = start;
347 gd->bd->bi_dram[current_bank].size = size;
353 int dram_init_banksize(void)
356 sc_faddr_t start, end, end1, end2;
360 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
361 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
363 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
364 err = get_owned_memreg(mr, &start, &end);
366 start = roundup(start, MEMSTART_ALIGNMENT);
367 if (start > end) /* Small memory region, no use it */
370 if (start >= PHYS_SDRAM_1 && start <= end1) {
371 gd->bd->bi_dram[i].start = start;
373 if ((end + 1) <= end1)
374 gd->bd->bi_dram[i].size =
377 gd->bd->bi_dram[i].size = end1 - start;
381 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
382 gd->bd->bi_dram[i].start = start;
384 if ((end + 1) <= end2)
385 gd->bd->bi_dram[i].size =
388 gd->bd->bi_dram[i].size = end2 - start;
396 /* If error, set to the default value */
398 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
399 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
400 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
401 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
407 static u64 get_block_attrs(sc_faddr_t addr_start)
409 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
410 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
412 if ((addr_start >= PHYS_SDRAM_1 &&
413 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
414 (addr_start >= PHYS_SDRAM_2 &&
415 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
416 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
421 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
423 sc_faddr_t end1, end2;
425 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
426 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
428 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
429 if ((addr_end + 1) > end1)
430 return end1 - addr_start;
431 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
432 if ((addr_end + 1) > end2)
433 return end2 - addr_start;
436 return (addr_end - addr_start + 1);
439 #define MAX_PTE_ENTRIES 512
440 #define MAX_MEM_MAP_REGIONS 16
442 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
443 struct mm_region *mem_map = imx8_mem_map;
445 void enable_caches(void)
448 sc_faddr_t start, end;
451 /* Create map for registers access from 0x1c000000 to 0x80000000*/
452 imx8_mem_map[0].virt = 0x1c000000UL;
453 imx8_mem_map[0].phys = 0x1c000000UL;
454 imx8_mem_map[0].size = 0x64000000UL;
455 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
456 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
459 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
460 err = get_owned_memreg(mr, &start, &end);
462 imx8_mem_map[i].virt = start;
463 imx8_mem_map[i].phys = start;
464 imx8_mem_map[i].size = get_block_size(start, end);
465 imx8_mem_map[i].attrs = get_block_attrs(start);
470 if (i < MAX_MEM_MAP_REGIONS) {
471 imx8_mem_map[i].size = 0;
472 imx8_mem_map[i].attrs = 0;
474 puts("Error, need more MEM MAP REGIONS reserved\n");
479 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
480 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
481 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
482 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
489 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
490 u64 get_page_table_size(void)
492 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
496 * For each memory region, the max table size:
497 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
499 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
502 * We need to duplicate our page table once to have an emergency pt to
503 * resort to when splitting page tables later on
508 * We may need to split page tables later on if dcache settings change,
509 * so reserve up to 4 (random pick) page tables for that.
517 #if defined(CONFIG_IMX8QM)
518 #define FUSE_MAC0_WORD0 452
519 #define FUSE_MAC0_WORD1 453
520 #define FUSE_MAC1_WORD0 454
521 #define FUSE_MAC1_WORD1 455
522 #elif defined(CONFIG_IMX8QXP)
523 #define FUSE_MAC0_WORD0 708
524 #define FUSE_MAC0_WORD1 709
525 #define FUSE_MAC1_WORD0 710
526 #define FUSE_MAC1_WORD1 711
529 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
531 u32 word[2], val[2] = {};
535 word[0] = FUSE_MAC0_WORD0;
536 word[1] = FUSE_MAC0_WORD1;
538 word[0] = FUSE_MAC1_WORD0;
539 word[1] = FUSE_MAC1_WORD1;
542 for (i = 0; i < 2; i++) {
543 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
549 mac[1] = val[0] >> 8;
550 mac[2] = val[0] >> 16;
551 mac[3] = val[0] >> 24;
553 mac[5] = val[1] >> 8;
555 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
556 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
559 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
562 u32 get_cpu_rev(void)
567 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
571 rev = (id >> 5) & 0xf;
572 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
574 return (id << 12) | rev;