1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
12 #include <dm/uclass.h>
15 #include <asm/arch/sci/sci.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch-imx/cpu.h>
18 #include <asm/armv8/cpu.h>
19 #include <asm/armv8/mmu.h>
20 #include <asm/mach-imx/boot_mode.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define BT_PASSOVER_TAG 0x504F
25 struct pass_over_info_t *get_pass_over_info(void)
27 struct pass_over_info_t *p =
28 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
30 if (p->barker != BT_PASSOVER_TAG ||
31 p->len != sizeof(struct pass_over_info_t))
37 int arch_cpu_init(void)
39 #ifdef CONFIG_SPL_BUILD
40 struct pass_over_info_t *pass_over;
42 if (is_soc_rev(CHIP_REV_A)) {
43 pass_over = get_pass_over_info();
44 if (pass_over && pass_over->g_ap_mu == 0) {
46 * When ap_mu is 0, means the U-Boot booted
47 * from first container
49 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
57 int arch_cpu_init_dm(void)
62 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
63 ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu",
64 offset_to_ofnode(node), &devp);
67 printf("could not find scu %d\n", ret);
71 ret = device_probe(devp);
73 printf("scu probe failed %d\n", ret);
80 int print_bootinfo(void)
82 enum boot_device bt_dev = get_boot_device();
117 printf("Unknown device %u\n", bt_dev);
124 enum boot_device get_boot_device(void)
126 enum boot_device boot_dev = SD1_BOOT;
130 sc_misc_get_boot_dev(-1, &dev_rsrc);
134 boot_dev = MMC1_BOOT;
143 boot_dev = NAND_BOOT;
146 boot_dev = FLEXSPI_BOOT;
149 boot_dev = SATA_BOOT;
163 #ifdef CONFIG_ENV_IS_IN_MMC
164 __weak int board_mmc_get_env_dev(int devno)
166 return CONFIG_SYS_MMC_ENV_DEV;
169 int mmc_get_env_dev(void)
174 sc_misc_get_boot_dev(-1, &dev_rsrc);
187 /* If not boot from sd/mmc, use default value */
188 return CONFIG_SYS_MMC_ENV_DEV;
191 return board_mmc_get_env_dev(devno);
195 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
197 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
198 sc_faddr_t *addr_end)
200 sc_faddr_t start, end;
204 owned = sc_rm_is_memreg_owned(-1, mr);
206 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
208 printf("Memreg get info failed, %d\n", ret);
211 debug("0x%llx -- 0x%llx\n", start, end);
221 phys_size_t get_effective_memsize(void)
224 sc_faddr_t start, end, end1;
227 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
229 for (mr = 0; mr < 64; mr++) {
230 err = get_owned_memreg(mr, &start, &end);
232 start = roundup(start, MEMSTART_ALIGNMENT);
233 /* Too small memory region, not use it */
237 /* Find the memory region runs the U-Boot */
238 if (start >= PHYS_SDRAM_1 && start <= end1 &&
239 (start <= CONFIG_SYS_TEXT_BASE &&
240 end >= CONFIG_SYS_TEXT_BASE)) {
241 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
243 return (end - PHYS_SDRAM_1 + 1);
245 return PHYS_SDRAM_1_SIZE;
250 return PHYS_SDRAM_1_SIZE;
256 sc_faddr_t start, end, end1, end2;
259 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
260 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
261 for (mr = 0; mr < 64; mr++) {
262 err = get_owned_memreg(mr, &start, &end);
264 start = roundup(start, MEMSTART_ALIGNMENT);
265 /* Too small memory region, not use it */
269 if (start >= PHYS_SDRAM_1 && start <= end1) {
270 if ((end + 1) <= end1)
271 gd->ram_size += end - start + 1;
273 gd->ram_size += end1 - start;
274 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
275 if ((end + 1) <= end2)
276 gd->ram_size += end - start + 1;
278 gd->ram_size += end2 - start;
283 /* If error, set to the default value */
285 gd->ram_size = PHYS_SDRAM_1_SIZE;
286 gd->ram_size += PHYS_SDRAM_2_SIZE;
291 static void dram_bank_sort(int current_bank)
296 while (current_bank > 0) {
297 if (gd->bd->bi_dram[current_bank - 1].start >
298 gd->bd->bi_dram[current_bank].start) {
299 start = gd->bd->bi_dram[current_bank - 1].start;
300 size = gd->bd->bi_dram[current_bank - 1].size;
302 gd->bd->bi_dram[current_bank - 1].start =
303 gd->bd->bi_dram[current_bank].start;
304 gd->bd->bi_dram[current_bank - 1].size =
305 gd->bd->bi_dram[current_bank].size;
307 gd->bd->bi_dram[current_bank].start = start;
308 gd->bd->bi_dram[current_bank].size = size;
314 int dram_init_banksize(void)
317 sc_faddr_t start, end, end1, end2;
321 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
322 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
324 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
325 err = get_owned_memreg(mr, &start, &end);
327 start = roundup(start, MEMSTART_ALIGNMENT);
328 if (start > end) /* Small memory region, no use it */
331 if (start >= PHYS_SDRAM_1 && start <= end1) {
332 gd->bd->bi_dram[i].start = start;
334 if ((end + 1) <= end1)
335 gd->bd->bi_dram[i].size =
338 gd->bd->bi_dram[i].size = end1 - start;
342 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
343 gd->bd->bi_dram[i].start = start;
345 if ((end + 1) <= end2)
346 gd->bd->bi_dram[i].size =
349 gd->bd->bi_dram[i].size = end2 - start;
357 /* If error, set to the default value */
359 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
360 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
361 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
362 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
368 static u64 get_block_attrs(sc_faddr_t addr_start)
370 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
371 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
373 if ((addr_start >= PHYS_SDRAM_1 &&
374 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
375 (addr_start >= PHYS_SDRAM_2 &&
376 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
377 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
382 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
384 sc_faddr_t end1, end2;
386 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
387 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
389 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
390 if ((addr_end + 1) > end1)
391 return end1 - addr_start;
392 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
393 if ((addr_end + 1) > end2)
394 return end2 - addr_start;
397 return (addr_end - addr_start + 1);
400 #define MAX_PTE_ENTRIES 512
401 #define MAX_MEM_MAP_REGIONS 16
403 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
404 struct mm_region *mem_map = imx8_mem_map;
406 void enable_caches(void)
409 sc_faddr_t start, end;
412 /* Create map for registers access from 0x1c000000 to 0x80000000*/
413 imx8_mem_map[0].virt = 0x1c000000UL;
414 imx8_mem_map[0].phys = 0x1c000000UL;
415 imx8_mem_map[0].size = 0x64000000UL;
416 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
417 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
420 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
421 err = get_owned_memreg(mr, &start, &end);
423 imx8_mem_map[i].virt = start;
424 imx8_mem_map[i].phys = start;
425 imx8_mem_map[i].size = get_block_size(start, end);
426 imx8_mem_map[i].attrs = get_block_attrs(start);
431 if (i < MAX_MEM_MAP_REGIONS) {
432 imx8_mem_map[i].size = 0;
433 imx8_mem_map[i].attrs = 0;
435 puts("Error, need more MEM MAP REGIONS reserved\n");
440 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
441 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
442 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
443 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
450 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
451 u64 get_page_table_size(void)
453 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
457 * For each memory region, the max table size:
458 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
460 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
463 * We need to duplicate our page table once to have an emergency pt to
464 * resort to when splitting page tables later on
469 * We may need to split page tables later on if dcache settings change,
470 * so reserve up to 4 (random pick) page tables for that.
478 #define FUSE_MAC0_WORD0 708
479 #define FUSE_MAC0_WORD1 709
480 #define FUSE_MAC1_WORD0 710
481 #define FUSE_MAC1_WORD1 711
483 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
485 u32 word[2], val[2] = {};
489 word[0] = FUSE_MAC0_WORD0;
490 word[1] = FUSE_MAC0_WORD1;
492 word[0] = FUSE_MAC1_WORD0;
493 word[1] = FUSE_MAC1_WORD1;
496 for (i = 0; i < 2; i++) {
497 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
503 mac[1] = val[0] >> 8;
504 mac[2] = val[0] >> 16;
505 mac[3] = val[0] >> 24;
507 mac[5] = val[1] >> 8;
509 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
510 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
513 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
516 u32 get_cpu_rev(void)
521 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
525 rev = (id >> 5) & 0xf;
526 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
528 return (id << 12) | rev;
531 #if CONFIG_IS_ENABLED(CPU)
532 struct cpu_imx_platdata {
540 const char *get_imx8_type(u32 imxtype)
543 case MXC_CPU_IMX8QXP:
544 case MXC_CPU_IMX8QXP_A0:
553 const char *get_imx8_rev(u32 rev)
565 const char *get_core_name(void)
569 else if (is_cortex_a53())
571 else if (is_cortex_a72())
577 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
578 static int cpu_imx_get_temp(void)
580 struct udevice *thermal_dev;
583 ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
587 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
597 static int cpu_imx_get_temp(void)
603 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
605 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
611 ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
612 plat->type, plat->rev, plat->name, plat->freq_mhz);
614 if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
617 ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
620 snprintf(buf + ret, size - ret, "\n");
625 static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
627 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
629 info->cpu_freq = plat->freq_mhz * 1000;
630 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
634 static int cpu_imx_get_count(struct udevice *dev)
639 static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size)
641 snprintf(buf, size, "NXP");
645 static const struct cpu_ops cpu_imx8_ops = {
646 .get_desc = cpu_imx_get_desc,
647 .get_info = cpu_imx_get_info,
648 .get_count = cpu_imx_get_count,
649 .get_vendor = cpu_imx_get_vendor,
652 static const struct udevice_id cpu_imx8_ids[] = {
653 { .compatible = "arm,cortex-a35" },
654 { .compatible = "arm,cortex-a53" },
658 static ulong imx8_get_cpu_rate(void)
662 int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
665 ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
666 (sc_pm_clock_rate_t *)&rate);
668 printf("Could not read CPU frequency: %d\n", ret);
675 static int imx8_cpu_probe(struct udevice *dev)
677 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
680 cpurev = get_cpu_rev();
681 plat->cpurev = cpurev;
682 plat->name = get_core_name();
683 plat->rev = get_imx8_rev(cpurev & 0xFFF);
684 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
685 plat->freq_mhz = imx8_get_cpu_rate() / 1000000;
689 U_BOOT_DRIVER(cpu_imx8_drv) = {
692 .of_match = cpu_imx8_ids,
693 .ops = &cpu_imx8_ops,
694 .probe = imx8_cpu_probe,
695 .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
696 .flags = DM_FLAG_PRE_RELOC,