arch/arm/mach-imx/imx8/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <cpu.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <event.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <asm/cache.h>
  15 #include <asm/global_data.h>
  16 #include <dm/device-internal.h>
  17 #include <dm/lists.h>
  18 #include <dm/uclass.h>
  19 #include <errno.h>
  20 #include <spl.h>
  21 #include <thermal.h>
  22 #include <asm/arch/sci/sci.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch-imx/cpu.h>
  25 #include <asm/armv8/cpu.h>
  26 #include <asm/armv8/mmu.h>
  27 #include <asm/setup.h>
  28 #include <asm/mach-imx/boot_mode.h>
  29 #include <spl.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define BT_PASSOVER_TAG 0x504F
  34 struct pass_over_info_t *get_pass_over_info(void)
  35 {
  36         struct pass_over_info_t *p =
  37                 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  38
  39         if (p->barker != BT_PASSOVER_TAG ||
  40             p->len != sizeof(struct pass_over_info_t))
  41                 return NULL;
  42
  43         return p;
  44 }
  45
  46 int arch_cpu_init(void)
  47 {
  48 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  49         spl_save_restore_data();
  50 #endif
  51
  52 #ifdef CONFIG_SPL_BUILD
  53         struct pass_over_info_t *pass_over;
  54
  55         if (is_soc_rev(CHIP_REV_A)) {
  56                 pass_over = get_pass_over_info();
  57                 if (pass_over && pass_over->g_ap_mu == 0) {
  58                         /*
  59                          * When ap_mu is 0, means the U-Boot booted
  60                          * from first container
  61                          */
  62                         sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  63                 }
  64         }
  65 #endif
  66
  67         return 0;
  68 }
  69
  70 static int imx8_init_mu(void *ctx, struct event *event)
  71 {
  72         struct udevice *devp;
  73         int node, ret;
  74
  75         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  76
  77         ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  78         if (ret) {
  79                 printf("could not get scu %d\n", ret);
  80                 return ret;
  81         }
  82
  83         if (is_imx8qm()) {
  84                 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  85                                                     SC_PM_PW_MODE_ON);
  86                 if (ret)
  87                         return ret;
  88         }
  89
  90         return 0;
  91 }
  92 EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
  93
  94 int print_bootinfo(void)
  95 {
  96         enum boot_device bt_dev = get_boot_device();
  97
  98         puts("Boot:  ");
  99         switch (bt_dev) {
 100         case SD1_BOOT:
 101                 puts("SD0\n");
 102                 break;
 103         case SD2_BOOT:
 104                 puts("SD1\n");
 105                 break;
 106         case SD3_BOOT:
 107                 puts("SD2\n");
 108                 break;
 109         case MMC1_BOOT:
 110                 puts("MMC0\n");
 111                 break;
 112         case MMC2_BOOT:
 113                 puts("MMC1\n");
 114                 break;
 115         case MMC3_BOOT:
 116                 puts("MMC2\n");
 117                 break;
 118         case FLEXSPI_BOOT:
 119                 puts("FLEXSPI\n");
 120                 break;
 121         case SATA_BOOT:
 122                 puts("SATA\n");
 123                 break;
 124         case NAND_BOOT:
 125                 puts("NAND\n");
 126                 break;
 127         case USB_BOOT:
 128                 puts("USB\n");
 129                 break;
 130         default:
 131                 printf("Unknown device %u\n", bt_dev);
 132                 break;
 133         }
 134
 135         return 0;
 136 }
 137
 138 enum boot_device get_boot_device(void)
 139 {
 140         enum boot_device boot_dev = SD1_BOOT;
 141
 142         sc_rsrc_t dev_rsrc;
 143
 144         sc_misc_get_boot_dev(-1, &dev_rsrc);
 145
 146         switch (dev_rsrc) {
 147         case SC_R_SDHC_0:
 148                 boot_dev = MMC1_BOOT;
 149                 break;
 150         case SC_R_SDHC_1:
 151                 boot_dev = SD2_BOOT;
 152                 break;
 153         case SC_R_SDHC_2:
 154                 boot_dev = SD3_BOOT;
 155                 break;
 156         case SC_R_NAND:
 157                 boot_dev = NAND_BOOT;
 158                 break;
 159         case SC_R_FSPI_0:
 160                 boot_dev = FLEXSPI_BOOT;
 161                 break;
 162         case SC_R_SATA_0:
 163                 boot_dev = SATA_BOOT;
 164                 break;
 165         case SC_R_USB_0:
 166         case SC_R_USB_1:
 167         case SC_R_USB_2:
 168                 boot_dev = USB_BOOT;
 169                 break;
 170         default:
 171                 break;
 172         }
 173
 174         return boot_dev;
 175 }
 176
 177 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 178 #define FUSE_UNIQUE_ID_WORD0 16
 179 #define FUSE_UNIQUE_ID_WORD1 17
 180 void get_board_serial(struct tag_serialnr *serialnr)
 181 {
 182         sc_err_t err;
 183         u32 val1 = 0, val2 = 0;
 184         u32 word1, word2;
 185
 186         if (!serialnr)
 187                 return;
 188
 189         word1 = FUSE_UNIQUE_ID_WORD0;
 190         word2 = FUSE_UNIQUE_ID_WORD1;
 191
 192         err = sc_misc_otp_fuse_read(-1, word1, &val1);
 193         if (err != SC_ERR_NONE) {
 194                 printf("%s fuse %d read error: %d\n", __func__, word1, err);
 195                 return;
 196         }
 197
 198         err = sc_misc_otp_fuse_read(-1, word2, &val2);
 199         if (err != SC_ERR_NONE) {
 200                 printf("%s fuse %d read error: %d\n", __func__, word2, err);
 201                 return;
 202         }
 203         serialnr->low = val1;
 204         serialnr->high = val2;
 205 }
 206 #endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/
 207
 208 #ifdef CONFIG_ENV_IS_IN_MMC
 209 __weak int board_mmc_get_env_dev(int devno)
 210 {
 211         return CONFIG_SYS_MMC_ENV_DEV;
 212 }
 213
 214 int mmc_get_env_dev(void)
 215 {
 216         sc_rsrc_t dev_rsrc;
 217         int devno;
 218
 219         sc_misc_get_boot_dev(-1, &dev_rsrc);
 220
 221         switch (dev_rsrc) {
 222         case SC_R_SDHC_0:
 223                 devno = 0;
 224                 break;
 225         case SC_R_SDHC_1:
 226                 devno = 1;
 227                 break;
 228         case SC_R_SDHC_2:
 229                 devno = 2;
 230                 break;
 231         default:
 232                 /* If not boot from sd/mmc, use default value */
 233                 return CONFIG_SYS_MMC_ENV_DEV;
 234         }
 235
 236         return board_mmc_get_env_dev(devno);
 237 }
 238 #endif
 239
 240 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 241
 242 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 243                             sc_faddr_t *addr_end)
 244 {
 245         sc_faddr_t start, end;
 246         int ret;
 247         bool owned;
 248
 249         owned = sc_rm_is_memreg_owned(-1, mr);
 250         if (owned) {
 251                 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
 252                 if (ret) {
 253                         printf("Memreg get info failed, %d\n", ret);
 254                         return -EINVAL;
 255                 }
 256                 debug("0x%llx -- 0x%llx\n", start, end);
 257                 *addr_start = start;
 258                 *addr_end = end;
 259
 260                 return 0;
 261         }
 262
 263         return -EINVAL;
 264 }
 265
 266 __weak void board_mem_get_layout(u64 *phys_sdram_1_start,
 267                                  u64 *phys_sdram_1_size,
 268                                  u64 *phys_sdram_2_start,
 269                                  u64 *phys_sdram_2_size)
 270 {
 271         *phys_sdram_1_start = PHYS_SDRAM_1;
 272         *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
 273         *phys_sdram_2_start = PHYS_SDRAM_2;
 274         *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
 275 }
 276
 277 phys_size_t get_effective_memsize(void)
 278 {
 279         sc_rm_mr_t mr;
 280         sc_faddr_t start, end, end1, start_aligned;
 281         u64 phys_sdram_1_start, phys_sdram_1_size;
 282         u64 phys_sdram_2_start, phys_sdram_2_size;
 283         int err;
 284
 285         board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
 286                              &phys_sdram_2_start, &phys_sdram_2_size);
 287
 288
 289         end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 290         for (mr = 0; mr < 64; mr++) {
 291                 err = get_owned_memreg(mr, &start, &end);
 292                 if (!err) {
 293                         start_aligned = roundup(start, MEMSTART_ALIGNMENT);
 294                         /* Too small memory region, not use it */
 295                         if (start_aligned > end)
 296                                 continue;
 297
 298                         /* Find the memory region runs the U-Boot */
 299                         if (start >= phys_sdram_1_start && start <= end1 &&
 300                             (start <= CONFIG_SYS_TEXT_BASE &&
 301                             end >= CONFIG_SYS_TEXT_BASE)) {
 302                                 if ((end + 1) <=
 303                                     ((sc_faddr_t)phys_sdram_1_start +
 304                                     phys_sdram_1_size))
 305                                         return (end - phys_sdram_1_start + 1);
 306                                 else
 307                                         return phys_sdram_1_size;
 308                         }
 309                 }
 310         }
 311
 312         return phys_sdram_1_size;
 313 }
 314
 315 int dram_init(void)
 316 {
 317         sc_rm_mr_t mr;
 318         sc_faddr_t start, end, end1, end2;
 319         u64 phys_sdram_1_start, phys_sdram_1_size;
 320         u64 phys_sdram_2_start, phys_sdram_2_size;
 321         int err;
 322
 323         board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
 324                              &phys_sdram_2_start, &phys_sdram_2_size);
 325
 326         end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 327         end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
 328         for (mr = 0; mr < 64; mr++) {
 329                 err = get_owned_memreg(mr, &start, &end);
 330                 if (!err) {
 331                         start = roundup(start, MEMSTART_ALIGNMENT);
 332                         /* Too small memory region, not use it */
 333                         if (start > end)
 334                                 continue;
 335
 336                         if (start >= phys_sdram_1_start && start <= end1) {
 337                                 if ((end + 1) <= end1)
 338                                         gd->ram_size += end - start + 1;
 339                                 else
 340                                         gd->ram_size += end1 - start;
 341                         } else if (start >= phys_sdram_2_start &&
 342                                    start <= end2) {
 343                                 if ((end + 1) <= end2)
 344                                         gd->ram_size += end - start + 1;
 345                                 else
 346                                         gd->ram_size += end2 - start;
 347                         }
 348                 }
 349         }
 350
 351         /* If error, set to the default value */
 352         if (!gd->ram_size) {
 353                 gd->ram_size = phys_sdram_1_size;
 354                 gd->ram_size += phys_sdram_2_size;
 355         }
 356         return 0;
 357 }
 358
 359 static void dram_bank_sort(int current_bank)
 360 {
 361         phys_addr_t start;
 362         phys_size_t size;
 363
 364         while (current_bank > 0) {
 365                 if (gd->bd->bi_dram[current_bank - 1].start >
 366                     gd->bd->bi_dram[current_bank].start) {
 367                         start = gd->bd->bi_dram[current_bank - 1].start;
 368                         size = gd->bd->bi_dram[current_bank - 1].size;
 369
 370                         gd->bd->bi_dram[current_bank - 1].start =
 371                                 gd->bd->bi_dram[current_bank].start;
 372                         gd->bd->bi_dram[current_bank - 1].size =
 373                                 gd->bd->bi_dram[current_bank].size;
 374
 375                         gd->bd->bi_dram[current_bank].start = start;
 376                         gd->bd->bi_dram[current_bank].size = size;
 377                 }
 378                 current_bank--;
 379         }
 380 }
 381
 382 int dram_init_banksize(void)
 383 {
 384         sc_rm_mr_t mr;
 385         sc_faddr_t start, end, end1, end2;
 386         int i = 0;
 387         u64 phys_sdram_1_start, phys_sdram_1_size;
 388         u64 phys_sdram_2_start, phys_sdram_2_size;
 389         int err;
 390
 391         board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
 392                              &phys_sdram_2_start, &phys_sdram_2_size);
 393
 394         end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 395         end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
 396         for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 397                 err = get_owned_memreg(mr, &start, &end);
 398                 if (!err) {
 399                         start = roundup(start, MEMSTART_ALIGNMENT);
 400                         if (start > end) /* Small memory region, no use it */
 401                                 continue;
 402
 403                         if (start >= phys_sdram_1_start && start <= end1) {
 404                                 gd->bd->bi_dram[i].start = start;
 405
 406                                 if ((end + 1) <= end1)
 407                                         gd->bd->bi_dram[i].size =
 408                                                 end - start + 1;
 409                                 else
 410                                         gd->bd->bi_dram[i].size = end1 - start;
 411
 412                                 dram_bank_sort(i);
 413                                 i++;
 414                         } else if (start >= phys_sdram_2_start && start <= end2) {
 415                                 gd->bd->bi_dram[i].start = start;
 416
 417                                 if ((end + 1) <= end2)
 418                                         gd->bd->bi_dram[i].size =
 419                                                 end - start + 1;
 420                                 else
 421                                         gd->bd->bi_dram[i].size = end2 - start;
 422
 423                                 dram_bank_sort(i);
 424                                 i++;
 425                         }
 426                 }
 427         }
 428
 429         /* If error, set to the default value */
 430         if (!i) {
 431                 gd->bd->bi_dram[0].start = phys_sdram_1_start;
 432                 gd->bd->bi_dram[0].size = phys_sdram_1_size;
 433                 gd->bd->bi_dram[1].start = phys_sdram_2_start;
 434                 gd->bd->bi_dram[1].size = phys_sdram_2_size;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static u64 get_block_attrs(sc_faddr_t addr_start)
 441 {
 442         u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
 443                 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 444         u64 phys_sdram_1_start, phys_sdram_1_size;
 445         u64 phys_sdram_2_start, phys_sdram_2_size;
 446
 447         board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
 448                              &phys_sdram_2_start, &phys_sdram_2_size);
 449
 450         if ((addr_start >= phys_sdram_1_start &&
 451              addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
 452             (addr_start >= phys_sdram_2_start &&
 453              addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
 454                 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
 455
 456         return attr;
 457 }
 458
 459 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
 460 {
 461         sc_faddr_t end1, end2;
 462         u64 phys_sdram_1_start, phys_sdram_1_size;
 463         u64 phys_sdram_2_start, phys_sdram_2_size;
 464
 465         board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
 466                              &phys_sdram_2_start, &phys_sdram_2_size);
 467
 468
 469         end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 470         end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
 471
 472         if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
 473                 if ((addr_end + 1) > end1)
 474                         return end1 - addr_start;
 475         } else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
 476                 if ((addr_end + 1) > end2)
 477                         return end2 - addr_start;
 478         }
 479
 480         return (addr_end - addr_start + 1);
 481 }
 482
 483 #define MAX_PTE_ENTRIES 512
 484 #define MAX_MEM_MAP_REGIONS 16
 485
 486 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
 487 struct mm_region *mem_map = imx8_mem_map;
 488
 489 void enable_caches(void)
 490 {
 491         sc_rm_mr_t mr;
 492         sc_faddr_t start, end;
 493         int err, i;
 494
 495         /* Create map for registers access from 0x1c000000 to 0x80000000*/
 496         imx8_mem_map[0].virt = 0x1c000000UL;
 497         imx8_mem_map[0].phys = 0x1c000000UL;
 498         imx8_mem_map[0].size = 0x64000000UL;
 499         imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 500                          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 501
 502         i = 1;
 503         for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 504                 err = get_owned_memreg(mr, &start, &end);
 505                 if (!err) {
 506                         imx8_mem_map[i].virt = start;
 507                         imx8_mem_map[i].phys = start;
 508                         imx8_mem_map[i].size = get_block_size(start, end);
 509                         imx8_mem_map[i].attrs = get_block_attrs(start);
 510                         i++;
 511                 }
 512         }
 513
 514         if (i < MAX_MEM_MAP_REGIONS) {
 515                 imx8_mem_map[i].size = 0;
 516                 imx8_mem_map[i].attrs = 0;
 517         } else {
 518                 puts("Error, need more MEM MAP REGIONS reserved\n");
 519                 icache_enable();
 520                 return;
 521         }
 522
 523         for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
 524                 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
 525                       i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
 526                       imx8_mem_map[i].size, imx8_mem_map[i].attrs);
 527         }
 528
 529         icache_enable();
 530         dcache_enable();
 531 }
 532
 533 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 534 u64 get_page_table_size(void)
 535 {
 536         u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
 537         u64 size = 0;
 538
 539         /*
 540          * For each memory region, the max table size:
 541          * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
 542          */
 543         size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
 544
 545         /*
 546          * We need to duplicate our page table once to have an emergency pt to
 547          * resort to when splitting page tables later on
 548          */
 549         size *= 2;
 550
 551         /*
 552          * We may need to split page tables later on if dcache settings change,
 553          * so reserve up to 4 (random pick) page tables for that.
 554          */
 555         size += one_pt * 4;
 556
 557         return size;
 558 }
 559 #endif
 560
 561 #if defined(CONFIG_IMX8QM)
 562 #define FUSE_MAC0_WORD0 452
 563 #define FUSE_MAC0_WORD1 453
 564 #define FUSE_MAC1_WORD0 454
 565 #define FUSE_MAC1_WORD1 455
 566 #elif defined(CONFIG_IMX8QXP)
 567 #define FUSE_MAC0_WORD0 708
 568 #define FUSE_MAC0_WORD1 709
 569 #define FUSE_MAC1_WORD0 710
 570 #define FUSE_MAC1_WORD1 711
 571 #endif
 572
 573 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 574 {
 575         u32 word[2], val[2] = {};
 576         int i, ret;
 577
 578         if (dev_id == 0) {
 579                 word[0] = FUSE_MAC0_WORD0;
 580                 word[1] = FUSE_MAC0_WORD1;
 581         } else {
 582                 word[0] = FUSE_MAC1_WORD0;
 583                 word[1] = FUSE_MAC1_WORD1;
 584         }
 585
 586         for (i = 0; i < 2; i++) {
 587                 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
 588                 if (ret < 0)
 589                         goto err;
 590         }
 591
 592         mac[0] = val[0];
 593         mac[1] = val[0] >> 8;
 594         mac[2] = val[0] >> 16;
 595         mac[3] = val[0] >> 24;
 596         mac[4] = val[1];
 597         mac[5] = val[1] >> 8;
 598
 599         debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
 600               __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 601         return;
 602 err:
 603         printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
 604 }
 605
 606 u32 get_cpu_rev(void)
 607 {
 608         u32 id = 0, rev = 0;
 609         int ret;
 610
 611         ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 612         if (ret)
 613                 return 0;
 614
 615         rev = (id >> 5)  & 0xf;
 616         id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 617
 618         return (id << 12) | rev;
 619 }
 620
 621 void board_boot_order(u32 *spl_boot_list)
 622 {
 623         spl_boot_list[0] = spl_boot_device();
 624
 625         if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
 626                 /* Check whether we own the flexspi0, if not, use NOR boot */
 627                 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
 628                         spl_boot_list[0] = BOOT_DEVICE_NOR;
 629         }
 630 }
 631
 632 bool m4_parts_booted(void)
 633 {
 634         sc_rm_pt_t m4_parts[2];
 635         int err;
 636
 637         err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
 638         if (err) {
 639                 printf("%s get resource [%d] owner error: %d\n", __func__,
 640                        SC_R_M4_0_PID0, err);
 641                 return false;
 642         }
 643
 644         if (sc_pm_is_partition_started(-1, m4_parts[0]))
 645                 return true;
 646
 647         if (is_imx8qm()) {
 648                 err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
 649                 if (err) {
 650                         printf("%s get resource [%d] owner error: %d\n",
 651                                __func__, SC_R_M4_1_PID0, err);
 652                         return false;
 653                 }
 654
 655                 if (sc_pm_is_partition_started(-1, m4_parts[1]))
 656                         return true;
 657         }
 658
 659         return false;
 660 }