1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
14 #include <linux/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <imx_thermal.h>
22 #include <ipu_pixfmt.h>
26 #ifdef CONFIG_FSL_ESDHC_IMX
27 #include <fsl_esdhc_imx.h>
30 static u32 reset_cause = -1;
32 u32 get_imx_reset_cause(void)
34 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
36 if (reset_cause == -1) {
37 reset_cause = readl(&src_regs->srsr);
38 /* preserve the value for U-Boot proper */
39 #if !defined(CONFIG_SPL_BUILD)
40 writel(reset_cause, &src_regs->srsr);
47 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
48 static char *get_reset_cause(void)
50 switch (get_imx_reset_cause()) {
75 #elif defined(CONFIG_IMX8M)
87 return "unknown reset";
92 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
94 const char *get_imx_type(u32 imxtype)
98 return "8MP"; /* Quad-core version of the imx8mp */
100 return "8MNano Quad"; /* Quad-core version */
101 case MXC_CPU_IMX8MND:
102 return "8MNano Dual"; /* Dual-core version */
103 case MXC_CPU_IMX8MNS:
104 return "8MNano Solo"; /* Single-core version */
105 case MXC_CPU_IMX8MNL:
106 return "8MNano QuadLite"; /* Quad-core Lite version */
107 case MXC_CPU_IMX8MNDL:
108 return "8MNano DualLite"; /* Dual-core Lite version */
109 case MXC_CPU_IMX8MNSL:
110 return "8MNano SoloLite"; /* Single-core Lite version */
112 return "8MMQ"; /* Quad-core version of the imx8mm */
113 case MXC_CPU_IMX8MML:
114 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
115 case MXC_CPU_IMX8MMD:
116 return "8MMD"; /* Dual-core version of the imx8mm */
117 case MXC_CPU_IMX8MMDL:
118 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
119 case MXC_CPU_IMX8MMS:
120 return "8MMS"; /* Single-core version of the imx8mm */
121 case MXC_CPU_IMX8MMSL:
122 return "8MMSL"; /* Single-core Lite version of the imx8mm */
124 return "8MQ"; /* Quad-core version of the imx8mq */
125 case MXC_CPU_IMX8MQL:
126 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
128 return "8MD"; /* Dual-core version of the imx8mq */
130 return "7S"; /* Single-core version of the mx7 */
132 return "7D"; /* Dual-core version of the mx7 */
134 return "6QP"; /* Quad-Plus version of the mx6 */
136 return "6DP"; /* Dual-Plus version of the mx6 */
138 return "6Q"; /* Quad-core version of the mx6 */
140 return "6D"; /* Dual-core version of the mx6 */
142 return "6DL"; /* Dual Lite version of the mx6 */
143 case MXC_CPU_MX6SOLO:
144 return "6SOLO"; /* Solo version of the mx6 */
146 return "6SL"; /* Solo-Lite version of the mx6 */
148 return "6SLL"; /* SLL version of the mx6 */
150 return "6SX"; /* SoloX version of the mx6 */
152 return "6UL"; /* Ultra-Lite version of the mx6 */
154 return "6ULL"; /* ULL version of the mx6 */
156 return "6ULZ"; /* ULZ version of the mx6 */
166 int print_cpuinfo(void)
169 __maybe_unused u32 max_freq;
171 cpurev = get_cpu_rev();
173 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
174 struct udevice *thermal_dev;
175 int cpu_tmp, minc, maxc, ret;
177 printf("CPU: Freescale i.MX%s rev%d.%d",
178 get_imx_type((cpurev & 0x1FF000) >> 12),
179 (cpurev & 0x000F0) >> 4,
180 (cpurev & 0x0000F) >> 0);
181 max_freq = get_cpu_speed_grade_hz();
182 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
183 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
185 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
186 mxc_get_clock(MXC_ARM_CLK) / 1000000);
189 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
190 get_imx_type((cpurev & 0x1FF000) >> 12),
191 (cpurev & 0x000F0) >> 4,
192 (cpurev & 0x0000F) >> 0,
193 mxc_get_clock(MXC_ARM_CLK) / 1000000);
196 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
198 switch (get_cpu_temp_grade(&minc, &maxc)) {
199 case TEMP_AUTOMOTIVE:
200 puts("Automotive temperature grade ");
202 case TEMP_INDUSTRIAL:
203 puts("Industrial temperature grade ");
205 case TEMP_EXTCOMMERCIAL:
206 puts("Extended Commercial temperature grade ");
209 puts("Commercial temperature grade ");
212 printf("(%dC to %dC)", minc, maxc);
213 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
215 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
218 printf(" at %dC\n", cpu_tmp);
220 debug(" - invalid sensor data\n");
222 debug(" - invalid sensor device\n");
226 printf("Reset cause: %s\n", get_reset_cause());
231 int cpu_eth_init(bd_t *bis)
235 #if defined(CONFIG_FEC_MXC)
236 rc = fecmxc_initialize(bis);
242 #ifdef CONFIG_FSL_ESDHC_IMX
244 * Initializes on-chip MMC controllers.
245 * to override, implement board_mmc_init()
247 int cpu_mmc_init(bd_t *bis)
249 return fsl_esdhc_mmc_init(bis);
253 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
254 u32 get_ahb_clk(void)
256 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
259 reg = __raw_readl(&imx_ccm->cbcdr);
260 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
261 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
263 return get_periph_clk() / (ahb_podf + 1);
267 void arch_preboot_os(void)
269 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
272 #if defined(CONFIG_SATA)
275 #if defined(CONFIG_MX6)
276 disable_sata_clock();
280 #if defined(CONFIG_VIDEO_IPUV3)
281 /* disable video before launching O/S */
284 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
290 void set_chipselect_size(int const cs_size)
293 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
294 reg = readl(&iomuxc_regs->gpr[1]);
298 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
301 case CS0_64M_CS1_64M:
302 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
305 case CS0_64M_CS1_32M_CS2_32M:
306 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
309 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
310 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
314 printf("Unknown chip select size: %d\n", cs_size);
318 writel(reg, &iomuxc_regs->gpr[1]);
322 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
324 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
325 * defines a 2-bit SPEED_GRADING
327 #define OCOTP_TESTER3_SPEED_SHIFT 8
329 OCOTP_TESTER3_SPEED_GRADE0,
330 OCOTP_TESTER3_SPEED_GRADE1,
331 OCOTP_TESTER3_SPEED_GRADE2,
332 OCOTP_TESTER3_SPEED_GRADE3,
333 OCOTP_TESTER3_SPEED_GRADE4,
336 u32 get_cpu_speed_grade_hz(void)
338 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
339 struct fuse_bank *bank = &ocotp->bank[1];
340 struct fuse_bank1_regs *fuse =
341 (struct fuse_bank1_regs *)bank->fuse_regs;
344 val = readl(&fuse->tester3);
345 val >>= OCOTP_TESTER3_SPEED_SHIFT;
347 if (is_imx8mn() || is_imx8mp()) {
349 return 2300000000 - val * 100000000;
358 case OCOTP_TESTER3_SPEED_GRADE0:
360 case OCOTP_TESTER3_SPEED_GRADE1:
361 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
362 case OCOTP_TESTER3_SPEED_GRADE2:
363 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
364 case OCOTP_TESTER3_SPEED_GRADE3:
365 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
366 case OCOTP_TESTER3_SPEED_GRADE4:
374 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
375 * defines a 2-bit SPEED_GRADING
377 #define OCOTP_TESTER3_TEMP_SHIFT 6
379 u32 get_cpu_temp_grade(int *minc, int *maxc)
381 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
382 struct fuse_bank *bank = &ocotp->bank[1];
383 struct fuse_bank1_regs *fuse =
384 (struct fuse_bank1_regs *)bank->fuse_regs;
387 val = readl(&fuse->tester3);
388 val >>= OCOTP_TESTER3_TEMP_SHIFT;
392 if (val == TEMP_AUTOMOTIVE) {
395 } else if (val == TEMP_INDUSTRIAL) {
398 } else if (val == TEMP_EXTCOMMERCIAL) {
410 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
411 enum boot_device get_boot_device(void)
413 struct bootrom_sw_info **p =
414 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
416 enum boot_device boot_dev = SD1_BOOT;
417 u8 boot_type = (*p)->boot_dev_type;
418 u8 boot_instance = (*p)->boot_dev_instance;
422 boot_dev = boot_instance + SD1_BOOT;
425 boot_dev = boot_instance + MMC1_BOOT;
428 boot_dev = NAND_BOOT;
431 boot_dev = QSPI_BOOT;
434 boot_dev = WEIM_NOR_BOOT;
436 case BOOT_TYPE_SPINOR:
437 boot_dev = SPI_NOR_BOOT;
452 #ifdef CONFIG_NXP_BOARD_REVISION
453 int nxp_board_rev(void)
456 * Get Board ID information from OCOTP_GP1[15:8]
461 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
462 struct fuse_bank *bank = &ocotp->bank[4];
463 struct fuse_bank4_regs *fuse =
464 (struct fuse_bank4_regs *)bank->fuse_regs;
466 return (readl(&fuse->gp1) >> 8 & 0x0F);
469 char nxp_board_rev_string(void)
471 const char *rev = "A";
473 return (*rev + nxp_board_rev() - 1);