1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
16 #include <linux/errno.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <imx_thermal.h>
24 #include <ipu_pixfmt.h>
27 #include <dm/device-internal.h>
28 #include <dm/uclass-internal.h>
30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h>
34 static u32 reset_cause = -1;
36 u32 get_imx_reset_cause(void)
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD)
44 writel(reset_cause, &src_regs->srsr);
51 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
52 static char *get_reset_cause(void)
54 switch (get_imx_reset_cause()) {
79 #elif defined(CONFIG_IMX8M)
91 return "unknown reset";
96 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
98 const char *get_imx_type(u32 imxtype)
102 return "8MP[8]"; /* Quad-core version of the imx8mp */
103 case MXC_CPU_IMX8MPD:
104 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
105 case MXC_CPU_IMX8MPL:
106 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
107 case MXC_CPU_IMX8MP6:
108 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
109 case MXC_CPU_IMX8MPUL:
110 return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
112 return "8MNano Quad"; /* Quad-core version */
113 case MXC_CPU_IMX8MND:
114 return "8MNano Dual"; /* Dual-core version */
115 case MXC_CPU_IMX8MNS:
116 return "8MNano Solo"; /* Single-core version */
117 case MXC_CPU_IMX8MNL:
118 return "8MNano QuadLite"; /* Quad-core Lite version */
119 case MXC_CPU_IMX8MNDL:
120 return "8MNano DualLite"; /* Dual-core Lite version */
121 case MXC_CPU_IMX8MNSL:
122 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
123 case MXC_CPU_IMX8MNUQ:
124 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
125 case MXC_CPU_IMX8MNUD:
126 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
127 case MXC_CPU_IMX8MNUS:
128 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
130 return "8MMQ"; /* Quad-core version of the imx8mm */
131 case MXC_CPU_IMX8MML:
132 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
133 case MXC_CPU_IMX8MMD:
134 return "8MMD"; /* Dual-core version of the imx8mm */
135 case MXC_CPU_IMX8MMDL:
136 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
137 case MXC_CPU_IMX8MMS:
138 return "8MMS"; /* Single-core version of the imx8mm */
139 case MXC_CPU_IMX8MMSL:
140 return "8MMSL"; /* Single-core Lite version of the imx8mm */
142 return "8MQ"; /* Quad-core version of the imx8mq */
143 case MXC_CPU_IMX8MQL:
144 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
146 return "8MD"; /* Dual-core version of the imx8mq */
148 return "7S"; /* Single-core version of the mx7 */
150 return "7D"; /* Dual-core version of the mx7 */
152 return "6QP"; /* Quad-Plus version of the mx6 */
154 return "6DP"; /* Dual-Plus version of the mx6 */
156 return "6Q"; /* Quad-core version of the mx6 */
158 return "6D"; /* Dual-core version of the mx6 */
160 return "6DL"; /* Dual Lite version of the mx6 */
161 case MXC_CPU_MX6SOLO:
162 return "6SOLO"; /* Solo version of the mx6 */
164 return "6SL"; /* Solo-Lite version of the mx6 */
166 return "6SLL"; /* SLL version of the mx6 */
168 return "6SX"; /* SoloX version of the mx6 */
170 return "6UL"; /* Ultra-Lite version of the mx6 */
172 return "6ULL"; /* ULL version of the mx6 */
174 return "6ULZ"; /* ULZ version of the mx6 */
184 int print_cpuinfo(void)
187 __maybe_unused u32 max_freq;
189 cpurev = get_cpu_rev();
191 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
192 struct udevice *thermal_dev;
193 int cpu_tmp, minc, maxc, ret;
195 printf("CPU: Freescale i.MX%s rev%d.%d",
196 get_imx_type((cpurev & 0x1FF000) >> 12),
197 (cpurev & 0x000F0) >> 4,
198 (cpurev & 0x0000F) >> 0);
199 max_freq = get_cpu_speed_grade_hz();
200 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
201 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
203 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
204 mxc_get_clock(MXC_ARM_CLK) / 1000000);
207 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
208 get_imx_type((cpurev & 0x1FF000) >> 12),
209 (cpurev & 0x000F0) >> 4,
210 (cpurev & 0x0000F) >> 0,
211 mxc_get_clock(MXC_ARM_CLK) / 1000000);
214 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
216 switch (get_cpu_temp_grade(&minc, &maxc)) {
217 case TEMP_AUTOMOTIVE:
218 puts("Automotive temperature grade ");
220 case TEMP_INDUSTRIAL:
221 puts("Industrial temperature grade ");
223 case TEMP_EXTCOMMERCIAL:
224 puts("Extended Commercial temperature grade ");
227 puts("Commercial temperature grade ");
230 printf("(%dC to %dC)", minc, maxc);
231 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
233 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
236 printf(" at %dC", cpu_tmp);
238 debug(" - invalid sensor data\n");
240 debug(" - invalid sensor device\n");
245 printf("Reset cause: %s\n", get_reset_cause());
250 int cpu_eth_init(struct bd_info *bis)
254 #if defined(CONFIG_FEC_MXC)
255 rc = fecmxc_initialize(bis);
261 #ifdef CONFIG_FSL_ESDHC_IMX
263 * Initializes on-chip MMC controllers.
264 * to override, implement board_mmc_init()
266 int cpu_mmc_init(struct bd_info *bis)
268 return fsl_esdhc_mmc_init(bis);
272 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
273 u32 get_ahb_clk(void)
275 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
278 reg = __raw_readl(&imx_ccm->cbcdr);
279 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
280 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
282 return get_periph_clk() / (ahb_podf + 1);
286 void arch_preboot_os(void)
288 #if defined(CONFIG_IMX_AHCI)
292 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
294 rc = device_remove(dev, DM_REMOVE_NORMAL);
296 printf("Cannot remove SATA device '%s' (err=%d)\n",
301 #if defined(CONFIG_SATA)
304 #if defined(CONFIG_MX6)
305 disable_sata_clock();
309 #if defined(CONFIG_VIDEO_IPUV3)
310 /* disable video before launching O/S */
313 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
319 void set_chipselect_size(int const cs_size)
322 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
323 reg = readl(&iomuxc_regs->gpr[1]);
327 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
330 case CS0_64M_CS1_64M:
331 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
334 case CS0_64M_CS1_32M_CS2_32M:
335 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
338 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
339 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
343 printf("Unknown chip select size: %d\n", cs_size);
347 writel(reg, &iomuxc_regs->gpr[1]);
351 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
353 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
354 * defines a 2-bit SPEED_GRADING
356 #define OCOTP_TESTER3_SPEED_SHIFT 8
358 OCOTP_TESTER3_SPEED_GRADE0,
359 OCOTP_TESTER3_SPEED_GRADE1,
360 OCOTP_TESTER3_SPEED_GRADE2,
361 OCOTP_TESTER3_SPEED_GRADE3,
362 OCOTP_TESTER3_SPEED_GRADE4,
365 u32 get_cpu_speed_grade_hz(void)
367 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
368 struct fuse_bank *bank = &ocotp->bank[1];
369 struct fuse_bank1_regs *fuse =
370 (struct fuse_bank1_regs *)bank->fuse_regs;
373 val = readl(&fuse->tester3);
374 val >>= OCOTP_TESTER3_SPEED_SHIFT;
376 if (is_imx8mn() || is_imx8mp()) {
378 return 2300000000 - val * 100000000;
387 case OCOTP_TESTER3_SPEED_GRADE0:
389 case OCOTP_TESTER3_SPEED_GRADE1:
390 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
391 case OCOTP_TESTER3_SPEED_GRADE2:
392 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
393 case OCOTP_TESTER3_SPEED_GRADE3:
394 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
395 case OCOTP_TESTER3_SPEED_GRADE4:
403 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
404 * defines a 2-bit SPEED_GRADING
406 #define OCOTP_TESTER3_TEMP_SHIFT 6
408 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
409 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
411 u32 get_cpu_temp_grade(int *minc, int *maxc)
413 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
414 struct fuse_bank *bank = &ocotp->bank[1];
415 struct fuse_bank1_regs *fuse =
416 (struct fuse_bank1_regs *)bank->fuse_regs;
419 val = readl(&fuse->tester3);
421 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
423 val >>= OCOTP_TESTER3_TEMP_SHIFT;
427 if (val == TEMP_AUTOMOTIVE) {
430 } else if (val == TEMP_INDUSTRIAL) {
433 } else if (val == TEMP_EXTCOMMERCIAL) {
445 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
446 enum boot_device get_boot_device(void)
448 struct bootrom_sw_info **p =
449 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
451 enum boot_device boot_dev = SD1_BOOT;
452 u8 boot_type = (*p)->boot_dev_type;
453 u8 boot_instance = (*p)->boot_dev_instance;
457 boot_dev = boot_instance + SD1_BOOT;
460 boot_dev = boot_instance + MMC1_BOOT;
463 boot_dev = NAND_BOOT;
466 boot_dev = QSPI_BOOT;
469 boot_dev = WEIM_NOR_BOOT;
471 case BOOT_TYPE_SPINOR:
472 boot_dev = SPI_NOR_BOOT;
479 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
480 boot_dev = QSPI_BOOT;
489 #ifdef CONFIG_NXP_BOARD_REVISION
490 int nxp_board_rev(void)
493 * Get Board ID information from OCOTP_GP1[15:8]
498 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
499 struct fuse_bank *bank = &ocotp->bank[4];
500 struct fuse_bank4_regs *fuse =
501 (struct fuse_bank4_regs *)bank->fuse_regs;
503 return (readl(&fuse->gp1) >> 8 & 0x0F);
506 char nxp_board_rev_string(void)
508 const char *rev = "A";
510 return (*rev + nxp_board_rev() - 1);