1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
16 #include <linux/errno.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <imx_thermal.h>
24 #include <ipu_pixfmt.h>
27 #include <dm/device-internal.h>
28 #include <dm/uclass-internal.h>
30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h>
34 static u32 reset_cause = -1;
36 u32 get_imx_reset_cause(void)
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD)
44 writel(reset_cause, &src_regs->srsr);
51 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
52 static char *get_reset_cause(void)
54 switch (get_imx_reset_cause()) {
79 #elif defined(CONFIG_IMX8M)
91 return "unknown reset";
96 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
98 const char *get_imx_type(u32 imxtype)
102 return "8MP[8]"; /* Quad-core version of the imx8mp */
103 case MXC_CPU_IMX8MPD:
104 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
105 case MXC_CPU_IMX8MPL:
106 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
107 case MXC_CPU_IMX8MP6:
108 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
110 return "8MNano Quad"; /* Quad-core version */
111 case MXC_CPU_IMX8MND:
112 return "8MNano Dual"; /* Dual-core version */
113 case MXC_CPU_IMX8MNS:
114 return "8MNano Solo"; /* Single-core version */
115 case MXC_CPU_IMX8MNL:
116 return "8MNano QuadLite"; /* Quad-core Lite version */
117 case MXC_CPU_IMX8MNDL:
118 return "8MNano DualLite"; /* Dual-core Lite version */
119 case MXC_CPU_IMX8MNSL:
120 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
121 case MXC_CPU_IMX8MNUQ:
122 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
123 case MXC_CPU_IMX8MNUD:
124 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
125 case MXC_CPU_IMX8MNUS:
126 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
128 return "8MMQ"; /* Quad-core version of the imx8mm */
129 case MXC_CPU_IMX8MML:
130 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
131 case MXC_CPU_IMX8MMD:
132 return "8MMD"; /* Dual-core version of the imx8mm */
133 case MXC_CPU_IMX8MMDL:
134 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
135 case MXC_CPU_IMX8MMS:
136 return "8MMS"; /* Single-core version of the imx8mm */
137 case MXC_CPU_IMX8MMSL:
138 return "8MMSL"; /* Single-core Lite version of the imx8mm */
140 return "8MQ"; /* Quad-core version of the imx8mq */
141 case MXC_CPU_IMX8MQL:
142 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
144 return "8MD"; /* Dual-core version of the imx8mq */
146 return "7S"; /* Single-core version of the mx7 */
148 return "7D"; /* Dual-core version of the mx7 */
150 return "6QP"; /* Quad-Plus version of the mx6 */
152 return "6DP"; /* Dual-Plus version of the mx6 */
154 return "6Q"; /* Quad-core version of the mx6 */
156 return "6D"; /* Dual-core version of the mx6 */
158 return "6DL"; /* Dual Lite version of the mx6 */
159 case MXC_CPU_MX6SOLO:
160 return "6SOLO"; /* Solo version of the mx6 */
162 return "6SL"; /* Solo-Lite version of the mx6 */
164 return "6SLL"; /* SLL version of the mx6 */
166 return "6SX"; /* SoloX version of the mx6 */
168 return "6UL"; /* Ultra-Lite version of the mx6 */
170 return "6ULL"; /* ULL version of the mx6 */
172 return "6ULZ"; /* ULZ version of the mx6 */
182 int print_cpuinfo(void)
185 __maybe_unused u32 max_freq;
187 cpurev = get_cpu_rev();
189 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
190 struct udevice *thermal_dev;
191 int cpu_tmp, minc, maxc, ret;
193 printf("CPU: Freescale i.MX%s rev%d.%d",
194 get_imx_type((cpurev & 0x1FF000) >> 12),
195 (cpurev & 0x000F0) >> 4,
196 (cpurev & 0x0000F) >> 0);
197 max_freq = get_cpu_speed_grade_hz();
198 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
199 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
201 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
202 mxc_get_clock(MXC_ARM_CLK) / 1000000);
205 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
206 get_imx_type((cpurev & 0x1FF000) >> 12),
207 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0,
209 mxc_get_clock(MXC_ARM_CLK) / 1000000);
212 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
214 switch (get_cpu_temp_grade(&minc, &maxc)) {
215 case TEMP_AUTOMOTIVE:
216 puts("Automotive temperature grade ");
218 case TEMP_INDUSTRIAL:
219 puts("Industrial temperature grade ");
221 case TEMP_EXTCOMMERCIAL:
222 puts("Extended Commercial temperature grade ");
225 puts("Commercial temperature grade ");
228 printf("(%dC to %dC)", minc, maxc);
229 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
231 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
234 printf(" at %dC", cpu_tmp);
236 debug(" - invalid sensor data\n");
238 debug(" - invalid sensor device\n");
243 printf("Reset cause: %s\n", get_reset_cause());
248 int cpu_eth_init(struct bd_info *bis)
252 #if defined(CONFIG_FEC_MXC)
253 rc = fecmxc_initialize(bis);
259 #ifdef CONFIG_FSL_ESDHC_IMX
261 * Initializes on-chip MMC controllers.
262 * to override, implement board_mmc_init()
264 int cpu_mmc_init(struct bd_info *bis)
266 return fsl_esdhc_mmc_init(bis);
270 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
271 u32 get_ahb_clk(void)
273 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
276 reg = __raw_readl(&imx_ccm->cbcdr);
277 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
278 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
280 return get_periph_clk() / (ahb_podf + 1);
284 void arch_preboot_os(void)
286 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
290 #if defined(CONFIG_IMX_AHCI)
294 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
296 rc = device_remove(dev, DM_REMOVE_NORMAL);
298 printf("Cannot remove SATA device '%s' (err=%d)\n",
303 #if defined(CONFIG_SATA)
306 #if defined(CONFIG_MX6)
307 disable_sata_clock();
311 #if defined(CONFIG_VIDEO_IPUV3)
312 /* disable video before launching O/S */
315 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
321 void set_chipselect_size(int const cs_size)
324 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
325 reg = readl(&iomuxc_regs->gpr[1]);
329 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
332 case CS0_64M_CS1_64M:
333 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
336 case CS0_64M_CS1_32M_CS2_32M:
337 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
340 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
341 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
345 printf("Unknown chip select size: %d\n", cs_size);
349 writel(reg, &iomuxc_regs->gpr[1]);
353 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
355 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
356 * defines a 2-bit SPEED_GRADING
358 #define OCOTP_TESTER3_SPEED_SHIFT 8
360 OCOTP_TESTER3_SPEED_GRADE0,
361 OCOTP_TESTER3_SPEED_GRADE1,
362 OCOTP_TESTER3_SPEED_GRADE2,
363 OCOTP_TESTER3_SPEED_GRADE3,
364 OCOTP_TESTER3_SPEED_GRADE4,
367 u32 get_cpu_speed_grade_hz(void)
369 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
370 struct fuse_bank *bank = &ocotp->bank[1];
371 struct fuse_bank1_regs *fuse =
372 (struct fuse_bank1_regs *)bank->fuse_regs;
375 val = readl(&fuse->tester3);
376 val >>= OCOTP_TESTER3_SPEED_SHIFT;
378 if (is_imx8mn() || is_imx8mp()) {
380 return 2300000000 - val * 100000000;
389 case OCOTP_TESTER3_SPEED_GRADE0:
391 case OCOTP_TESTER3_SPEED_GRADE1:
392 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
393 case OCOTP_TESTER3_SPEED_GRADE2:
394 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
395 case OCOTP_TESTER3_SPEED_GRADE3:
396 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
397 case OCOTP_TESTER3_SPEED_GRADE4:
405 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
406 * defines a 2-bit SPEED_GRADING
408 #define OCOTP_TESTER3_TEMP_SHIFT 6
410 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
411 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
413 u32 get_cpu_temp_grade(int *minc, int *maxc)
415 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
416 struct fuse_bank *bank = &ocotp->bank[1];
417 struct fuse_bank1_regs *fuse =
418 (struct fuse_bank1_regs *)bank->fuse_regs;
421 val = readl(&fuse->tester3);
423 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
425 val >>= OCOTP_TESTER3_TEMP_SHIFT;
429 if (val == TEMP_AUTOMOTIVE) {
432 } else if (val == TEMP_INDUSTRIAL) {
435 } else if (val == TEMP_EXTCOMMERCIAL) {
447 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
448 enum boot_device get_boot_device(void)
450 struct bootrom_sw_info **p =
451 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
453 enum boot_device boot_dev = SD1_BOOT;
454 u8 boot_type = (*p)->boot_dev_type;
455 u8 boot_instance = (*p)->boot_dev_instance;
459 boot_dev = boot_instance + SD1_BOOT;
462 boot_dev = boot_instance + MMC1_BOOT;
465 boot_dev = NAND_BOOT;
468 boot_dev = QSPI_BOOT;
471 boot_dev = WEIM_NOR_BOOT;
473 case BOOT_TYPE_SPINOR:
474 boot_dev = SPI_NOR_BOOT;
481 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
482 boot_dev = QSPI_BOOT;
491 #ifdef CONFIG_NXP_BOARD_REVISION
492 int nxp_board_rev(void)
495 * Get Board ID information from OCOTP_GP1[15:8]
500 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
501 struct fuse_bank *bank = &ocotp->bank[4];
502 struct fuse_bank4_regs *fuse =
503 (struct fuse_bank4_regs *)bank->fuse_regs;
505 return (readl(&fuse->gp1) >> 8 & 0x0F);
508 char nxp_board_rev_string(void)
510 const char *rev = "A";
512 return (*rev + nxp_board_rev() - 1);