1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
10 #include <asm/global_data.h>
12 #include <asm/cache.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/dmc.h>
16 #include <asm/arch/periph.h>
17 #include <asm/arch/pinmux.h>
18 #include <asm/arch/power.h>
19 #include <asm/arch/spl.h>
20 #include <asm/arch/spi.h>
22 #include "common_setup.h"
23 #include "clock_init.h"
25 #ifdef CONFIG_ARCH_EXYNOS5
26 #define SECURE_BL1_ONLY
28 /* Secure FW size configuration */
29 #ifdef SECURE_BL1_ONLY
30 #define SEC_FW_SIZE (8 << 10) /* 8KB */
35 /* Configuration of BL1, BL2, ENV Blocks on mmc */
36 #define RES_BLOCK_SIZE (512)
37 #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
38 #define BL2_SIZE (512UL << 10UL) /* 512 KB */
40 #define BL1_OFFSET (RES_BLOCK_SIZE + SEC_FW_SIZE)
41 #define BL2_OFFSET (BL1_OFFSET + BL1_SIZE)
43 /* U-Boot copy size from boot Media to DRAM.*/
44 #define BL2_START_OFFSET (BL2_OFFSET/512)
45 #define BL2_SIZE_BLOC_COUNT (BL2_SIZE/512)
47 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
48 #define SPI_FLASH_UBOOT_POS (SEC_FW_SIZE + BL1_SIZE)
49 #elif defined(CONFIG_ARCH_EXYNOS4)
50 #define COPY_BL2_SIZE 0x80000
51 #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
52 #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
55 DECLARE_GLOBAL_DATA_PTR;
57 /* Index into irom ptr table */
66 /* IROM Function Pointers Table */
67 u32 irom_ptr_table[] = {
68 [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
69 [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
70 [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
71 -EMMC4.4 end boot operation */
72 [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
73 [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
76 void *get_irom_func(int index)
78 return (void *)*(u32 *)irom_ptr_table[index];
81 #ifdef CONFIG_USB_BOOTING
83 * Set/clear program flow prediction and return the previous state.
85 static int config_branch_prediction(int set_cr_z)
89 /* System Control Register: 11th bit Z Branch prediction enable */
91 set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
97 #ifdef CONFIG_SPI_BOOTING
98 static void spi_rx_tx(struct exynos_spi *regs, int todo,
99 void *dinp, void const *doutp, int i)
101 uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
103 uint out_bytes, in_bytes;
107 setbits_le32(®s->ch_cfg, SPI_CH_RST);
108 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
109 writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
115 spi_sts = readl(®s->spi_sts);
116 rx_lvl = ((spi_sts >> 15) & 0x7f);
117 tx_lvl = ((spi_sts >> 6) & 0x7f);
118 while (tx_lvl < 32 && out_bytes) {
120 writel(temp, ®s->tx_data);
124 while (rx_lvl >= 4 && in_bytes) {
125 temp = readl(®s->rx_data);
135 * Copy uboot from spi flash to RAM
137 * @parma uboot_size size of u-boot to copy
138 * @param uboot_addr address in u-boot to copy
140 static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
143 int i, timeout = 100;
144 struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
146 set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
147 /* set the spi1 GPIO */
148 exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
150 /* set pktcnt and enable it */
151 writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
153 writel(SPI_FB_DELAY_180, ®s->fb_clk);
154 /* set CH_WIDTH and BUS_WIDTH as word */
155 setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
156 SPI_MODE_BUS_WIDTH_WORD);
157 clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
159 /* clear rx and tx channel if set priveously */
160 clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
162 setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN |
166 /* do a soft reset */
167 setbits_le32(®s->ch_cfg, SPI_CH_RST);
168 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
170 /* now set rx and tx channel ON */
171 setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
172 clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
174 /* Send read instruction (0x3h) followed by a 24 bit addr */
175 writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data);
177 /* waiting for TX done */
178 while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) {
180 debug("SPI TIMEOUT\n");
186 for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
187 todo = min(uboot_size - upto, (unsigned int)(1 << 15));
188 spi_rx_tx(regs, todo, (void *)(uboot_addr),
189 (void *)(SPI_FLASH_UBOOT_POS), i);
192 setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
195 * Let put controller mode to BYTE as
196 * SPI driver does not support WORD mode yet
198 clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
199 SPI_MODE_BUS_WIDTH_WORD);
200 writel(0, ®s->swap_cfg);
203 * Flush spi tx, rx fifos and reset the SPI controller
204 * and clear rx/tx channel
206 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
207 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
208 clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
213 * Copy U-Boot from mmc to RAM:
214 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
215 * Pointer to API (Data transfer from mmc to ram)
217 void copy_uboot_to_ram(void)
219 unsigned int bootmode = BOOT_MODE_OM;
221 u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
222 u32 offset = 0, size = 0;
223 #ifdef CONFIG_SPI_BOOTING
224 struct spl_machine_param *param = spl_get_machine_params();
226 #ifdef CONFIG_SUPPORT_EMMC_BOOT
227 u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
228 void (*end_bootop_from_emmc)(void);
230 #ifdef CONFIG_USB_BOOTING
232 unsigned int sec_boot_check;
235 * Note that older hardware (before Exynos5800) does not expect any
236 * arguments, but it does not hurt to pass them, so a common function
239 u32 (*usb_copy)(u32 num_of_block, u32 *dst);
241 /* Read iRAM location to check for secondary USB boot mode */
242 sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
243 if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
244 bootmode = BOOT_MODE_USB;
247 if (bootmode == BOOT_MODE_OM)
248 bootmode = get_boot_mode();
251 #ifdef CONFIG_SPI_BOOTING
252 case BOOT_MODE_SERIAL:
253 /* Customised function to copy u-boot from SF */
254 exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
258 offset = BL2_START_OFFSET;
259 size = BL2_SIZE_BLOC_COUNT;
260 copy_bl2 = get_irom_func(MMC_INDEX);
262 #ifdef CONFIG_SUPPORT_EMMC_BOOT
264 /* Set the FSYS1 clock divisor value for EMMC boot */
265 emmc_boot_clk_div_set();
267 copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
268 end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
270 copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
271 end_bootop_from_emmc();
274 #ifdef CONFIG_USB_BOOTING
277 * iROM needs program flow prediction to be disabled
278 * before copy from USB device to RAM
280 is_cr_z_set = config_branch_prediction(0);
281 usb_copy = get_irom_func(USB_INDEX);
282 usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
283 config_branch_prediction(is_cr_z_set);
291 copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
294 void memzero(void *s, size_t n)
299 for (i = 0; i < n; i++)
304 * Set up the U-Boot global_data pointer
306 * This sets the address of the global data, and sets up basic values.
308 * @param gdp Value to give to gd
310 static void setup_global_data(gd_t *gdp)
313 memzero((void *)gd, sizeof(gd_t));
314 gd->flags |= GD_FLG_RELOC;
315 gd->baudrate = CONFIG_BAUDRATE;
316 gd->have_console = 1;
319 void board_init_f(unsigned long bootflag)
321 __aligned(8) gd_t local_gd;
322 __attribute__((noreturn)) void (*uboot)(void);
324 setup_global_data(&local_gd);
326 if (do_lowlevel_init())
331 /* Jump to U-Boot image */
332 uboot = (void *)CONFIG_SYS_TEXT_BASE;
334 /* Never returns Here */
338 void board_init_r(gd_t *id, ulong dest_addr)
340 /* Function attribute is no-return */
341 /* This Function never executes */