1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
4 * Donghwa Lee <dh09.lee@samsung.com>
9 #include <asm/arch/power.h>
11 static void exynos4_mipi_phy_control(unsigned int dev_index,
14 struct exynos4_power *pmu =
15 (struct exynos4_power *)samsung_get_base_power();
16 unsigned int addr, cfg = 0;
19 addr = (unsigned int)&pmu->mipi_phy0_control;
21 addr = (unsigned int)&pmu->mipi_phy1_control;
26 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
28 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
33 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
36 exynos4_mipi_phy_control(dev_index, enable);
39 void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
41 struct exynos5_power *power =
42 (struct exynos5_power *)samsung_get_base_power();
45 /* Enabling USBHOST_PHY */
46 setbits_le32(&power->usbhost_phy_control,
47 POWER_USB_HOST_PHY_CTRL_EN);
49 /* Disabling USBHOST_PHY */
50 clrbits_le32(&power->usbhost_phy_control,
51 POWER_USB_HOST_PHY_CTRL_EN);
55 void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
57 struct exynos4412_power *power =
58 (struct exynos4412_power *)samsung_get_base_power();
61 /* Enabling USBHOST_PHY */
62 setbits_le32(&power->usbhost_phy_control,
63 POWER_USB_HOST_PHY_CTRL_EN);
64 setbits_le32(&power->hsic1_phy_control,
65 POWER_USB_HOST_PHY_CTRL_EN);
66 setbits_le32(&power->hsic2_phy_control,
67 POWER_USB_HOST_PHY_CTRL_EN);
69 /* Disabling USBHOST_PHY */
70 clrbits_le32(&power->usbhost_phy_control,
71 POWER_USB_HOST_PHY_CTRL_EN);
72 clrbits_le32(&power->hsic1_phy_control,
73 POWER_USB_HOST_PHY_CTRL_EN);
74 clrbits_le32(&power->hsic2_phy_control,
75 POWER_USB_HOST_PHY_CTRL_EN);
79 void set_usbhost_phy_ctrl(unsigned int enable)
82 exynos5_set_usbhost_phy_ctrl(enable);
83 else if (cpu_is_exynos4())
84 if (proid_is_exynos4412())
85 exynos4412_set_usbhost_phy_ctrl(enable);
88 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
90 struct exynos5_power *power =
91 (struct exynos5_power *)samsung_get_base_power();
94 /* Enabling USBDRD_PHY */
95 setbits_le32(&power->usbdrd_phy_control,
96 POWER_USB_DRD_PHY_CTRL_EN);
98 /* Disabling USBDRD_PHY */
99 clrbits_le32(&power->usbdrd_phy_control,
100 POWER_USB_DRD_PHY_CTRL_EN);
104 static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
106 struct exynos5420_power *power =
107 (struct exynos5420_power *)samsung_get_base_power();
110 /* Enabling USBDEV_PHY */
111 setbits_le32(&power->usbdev_phy_control,
112 POWER_USB_DRD_PHY_CTRL_EN);
113 setbits_le32(&power->usbdev1_phy_control,
114 POWER_USB_DRD_PHY_CTRL_EN);
116 /* Disabling USBDEV_PHY */
117 clrbits_le32(&power->usbdev_phy_control,
118 POWER_USB_DRD_PHY_CTRL_EN);
119 clrbits_le32(&power->usbdev1_phy_control,
120 POWER_USB_DRD_PHY_CTRL_EN);
124 void set_usbdrd_phy_ctrl(unsigned int enable)
126 if (cpu_is_exynos5()) {
127 if (proid_is_exynos542x())
128 exynos5420_set_usbdev_phy_ctrl(enable);
130 exynos5_set_usbdrd_phy_ctrl(enable);
134 static void exynos5_dp_phy_control(unsigned int enable)
137 struct exynos5_power *power =
138 (struct exynos5_power *)samsung_get_base_power();
140 cfg = readl(&power->dptx_phy_control);
142 cfg |= EXYNOS_DP_PHY_ENABLE;
144 cfg &= ~EXYNOS_DP_PHY_ENABLE;
146 writel(cfg, &power->dptx_phy_control);
149 void exynos_dp_phy_ctrl(unsigned int enable)
151 if (cpu_is_exynos5())
152 exynos5_dp_phy_control(enable);
155 static void exynos5_set_ps_hold_ctrl(void)
157 struct exynos5_power *power =
158 (struct exynos5_power *)samsung_get_base_power();
160 /* Set PS-Hold high */
161 setbits_le32(&power->ps_hold_control,
162 EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
166 * Set ps_hold data driving value high
167 * This enables the machine to stay powered on
168 * after the initial power-on condition goes away
169 * (e.g. power button).
171 void set_ps_hold_ctrl(void)
173 if (cpu_is_exynos5())
174 exynos5_set_ps_hold_ctrl();
178 static void exynos5_set_xclkout(void)
180 struct exynos5_power *power =
181 (struct exynos5_power *)samsung_get_base_power();
183 /* use xxti for xclk out */
184 clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
188 void set_xclkout(void)
190 if (cpu_is_exynos5())
191 exynos5_set_xclkout();
194 /* Enables hardware tripping to power off the system when TMU fails */
195 void set_hw_thermal_trip(void)
197 if (cpu_is_exynos5()) {
198 struct exynos5_power *power =
199 (struct exynos5_power *)samsung_get_base_power();
201 /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
202 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
206 static uint32_t exynos5_get_reset_status(void)
208 struct exynos5_power *power =
209 (struct exynos5_power *)samsung_get_base_power();
211 return power->inform1;
214 static uint32_t exynos4_get_reset_status(void)
216 struct exynos4_power *power =
217 (struct exynos4_power *)samsung_get_base_power();
219 return power->inform1;
222 uint32_t get_reset_status(void)
224 if (cpu_is_exynos5())
225 return exynos5_get_reset_status();
227 return exynos4_get_reset_status();
230 static void exynos5_power_exit_wakeup(void)
232 struct exynos5_power *power =
233 (struct exynos5_power *)samsung_get_base_power();
234 typedef void (*resume_func)(void);
236 ((resume_func)power->inform0)();
239 static void exynos4_power_exit_wakeup(void)
241 struct exynos4_power *power =
242 (struct exynos4_power *)samsung_get_base_power();
243 typedef void (*resume_func)(void);
245 ((resume_func)power->inform0)();
248 void power_exit_wakeup(void)
250 if (cpu_is_exynos5())
251 exynos5_power_exit_wakeup();
253 exynos4_power_exit_wakeup();
256 unsigned int get_boot_mode(void)
258 unsigned int om_pin = samsung_get_base_power();
260 return readl(om_pin) & OM_PIN_MASK;