2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Power Management support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/smp_scu.h>
30 #include <plat/regs-srom.h>
32 #include <mach/regs-irq.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/regs-clock.h>
35 #include <mach/regs-pmu.h>
36 #include <mach/pm-core.h>
39 static struct sleep_save exynos4_set_clksrc[] = {
40 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
41 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
45 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
46 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
48 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
51 static struct sleep_save exynos4210_set_clksrc[] = {
52 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
55 static struct sleep_save exynos4_epll_save[] = {
56 SAVE_ITEM(EXYNOS4_EPLL_CON0),
57 SAVE_ITEM(EXYNOS4_EPLL_CON1),
60 static struct sleep_save exynos4_vpll_save[] = {
61 SAVE_ITEM(EXYNOS4_VPLL_CON0),
62 SAVE_ITEM(EXYNOS4_VPLL_CON1),
65 static struct sleep_save exynos_core_save[] = {
67 SAVE_ITEM(S5P_SROM_BW),
68 SAVE_ITEM(S5P_SROM_BC0),
69 SAVE_ITEM(S5P_SROM_BC1),
70 SAVE_ITEM(S5P_SROM_BC2),
71 SAVE_ITEM(S5P_SROM_BC3),
75 /* For Cortex-A9 Diagnostic and Power control register */
76 static unsigned int save_arm_register[2];
78 static int exynos_cpu_suspend(unsigned long arg)
80 #ifdef CONFIG_CACHE_L2X0
84 if (soc_is_exynos5250())
87 /* issue the standby signal into the pm unit. */
90 /* we should never get past here */
91 panic("sleep resumed to originator?");
94 static void exynos_pm_prepare(void)
98 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
100 if (!soc_is_exynos5250()) {
101 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
102 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
104 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
105 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
106 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
107 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
110 /* Set value of power down register for sleep mode */
112 exynos_sys_powerdown_conf(SYS_SLEEP);
113 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
115 /* ensure at least INFORM0 has the resume address */
117 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
119 /* Before enter central sequence mode, clock src register have to set */
121 if (!soc_is_exynos5250())
122 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
124 if (soc_is_exynos4210())
125 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
129 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
131 pm_cpu_prep = exynos_pm_prepare;
132 pm_cpu_sleep = exynos_cpu_suspend;
137 static unsigned long pll_base_rate;
139 static void exynos4_restore_pll(void)
141 unsigned long pll_con, locktime, lockcnt;
142 unsigned long pll_in_rate;
143 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
145 if (pll_base_rate == 0)
148 pll_in_rate = pll_base_rate;
151 pll_con = exynos4_epll_save[0].val;
153 if (pll_con & (1 << 31)) {
154 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
155 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
157 pll_in_rate /= 1000000;
159 locktime = (3000 / pll_in_rate) * p_div;
160 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
162 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
164 s3c_pm_do_restore_core(exynos4_epll_save,
165 ARRAY_SIZE(exynos4_epll_save));
169 pll_in_rate = pll_base_rate;
172 pll_con = exynos4_vpll_save[0].val;
174 if (pll_con & (1 << 31)) {
175 pll_in_rate /= 1000000;
178 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
180 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
182 s3c_pm_do_restore_core(exynos4_vpll_save,
183 ARRAY_SIZE(exynos4_vpll_save));
187 /* Wait PLL locking */
191 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
192 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
197 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
198 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
201 } while (epll_wait || vpll_wait);
204 static struct subsys_interface exynos_pm_interface = {
206 .subsys = &exynos_subsys,
207 .add_dev = exynos_pm_add,
210 static __init int exynos_pm_drvinit(void)
212 struct clk *pll_base;
217 /* All wakeup disable */
219 tmp = __raw_readl(S5P_WAKEUP_MASK);
220 tmp |= ((0xFF << 8) | (0x1F << 1));
221 __raw_writel(tmp, S5P_WAKEUP_MASK);
223 if (!soc_is_exynos5250()) {
224 pll_base = clk_get(NULL, "xtal");
226 if (!IS_ERR(pll_base)) {
227 pll_base_rate = clk_get_rate(pll_base);
232 return subsys_interface_register(&exynos_pm_interface);
234 arch_initcall(exynos_pm_drvinit);
236 static int exynos_pm_suspend(void)
240 /* Setting Central Sequence Register for power down mode */
242 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
243 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
244 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
246 /* Setting SEQ_OPTION register */
248 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
249 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
251 if (!soc_is_exynos5250()) {
252 /* Save Power control register */
253 asm ("mrc p15, 0, %0, c15, c0, 0"
254 : "=r" (tmp) : : "cc");
255 save_arm_register[0] = tmp;
257 /* Save Diagnostic register */
258 asm ("mrc p15, 0, %0, c15, c0, 1"
259 : "=r" (tmp) : : "cc");
260 save_arm_register[1] = tmp;
266 static void exynos_pm_resume(void)
271 * If PMU failed while entering sleep mode, WFI will be
272 * ignored by PMU and then exiting cpu_do_idle().
273 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
276 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
277 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
278 tmp |= S5P_CENTRAL_LOWPWR_CFG;
279 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
280 /* No need to perform below restore code */
283 if (!soc_is_exynos5250()) {
284 /* Restore Power control register */
285 tmp = save_arm_register[0];
286 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
290 /* Restore Diagnostic register */
291 tmp = save_arm_register[1];
292 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
297 /* For release retention */
299 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
300 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
301 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
302 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
303 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
304 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
305 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
307 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
309 if (!soc_is_exynos5250()) {
310 exynos4_restore_pll();
313 scu_enable(S5P_VA_SCU);
319 /* Clear SLEEP mode set in INFORM1 */
320 __raw_writel(0x0, S5P_INFORM1);
325 static struct syscore_ops exynos_pm_syscore_ops = {
326 .suspend = exynos_pm_suspend,
327 .resume = exynos_pm_resume,
330 static __init int exynos_pm_syscore_init(void)
332 register_syscore_ops(&exynos_pm_syscore_ops);
335 arch_initcall(exynos_pm_syscore_init);