2 * Lowlevel setup for EXYNOS5 based board
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <debug_uart.h>
29 #include <asm/system.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/dmc.h>
32 #include <asm/arch/power.h>
33 #include <asm/arch/tzpc.h>
34 #include <asm/arch/periph.h>
35 #include <asm/arch/pinmux.h>
36 #include <asm/arch/system.h>
37 #include <asm/armv7.h>
38 #include "common_setup.h"
39 #include "exynos5_setup.h"
41 /* These are the things we can do during low-level init */
45 DO_MEM_RESET = 1 << 2,
50 #ifdef CONFIG_EXYNOS5420
52 * Power up secondary CPUs.
54 static void secondary_cpu_start(void)
56 v7_enable_smp(EXYNOS5420_INFORM_BASE);
58 branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
62 * This is the entry point of hotplug-in and
65 static void low_power_start(void)
67 uint32_t val, reg_val;
69 reg_val = readl(EXYNOS5420_SPARE_BASE);
70 if (reg_val != CPU_RST_FLAG_VAL) {
71 writel(0x0, CONFIG_LOWPOWER_FLAG);
75 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
76 if (reg_val != (uint32_t)&low_power_start) {
77 /* Store jump address as low_power_start if not present */
78 writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
83 /* Set the CPU to SVC32 mode */
86 #ifndef CONFIG_SYS_L2CACHE_OFF
87 /* Read MIDR for Primary Part Number */
95 v7_enable_l2_hazard_detect();
99 /* Invalidate L1 & TLB */
104 /* Disable MMU stuff and caches */
107 val &= ~((0x2 << 12) | 0x7);
108 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
111 /* CPU state is hotplug or reset */
112 secondary_cpu_start();
114 /* Core should not enter into WFI here */
119 * Pointer to this function is stored in iRam which is used
120 * for jump and power down of a specific core.
122 static void power_down_core(void)
124 uint32_t tmp, core_id, core_config;
126 /* Get the unique core id */
128 * Multiprocessor Affinity Register
134 core_id = (core_id >> 6) & ~3;
138 /* Set the status of the core to low */
139 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
140 core_config += EXYNOS5420_CPU_CONFIG_BASE;
141 writel(0x0, core_config);
148 * Configurations for secondary cores are inapt at this stage.
149 * Reconfigure secondary cores. Shutdown and change the status
150 * of all cores except the primary core.
152 static void secondary_cores_configure(void)
154 /* Clear secondary boot iRAM base */
155 writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
157 /* set lowpower flag and address */
158 writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
159 writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
160 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
161 /* Store jump address for power down */
162 writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
164 /* Need all core power down check */
169 extern void relocate_wait_code(void);
172 int do_lowlevel_init(void)
174 uint32_t reset_status;
179 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
181 * Init L2 cache parameters here for use by boot and resume
183 * These are here instead of in v7_outer_cache_enable() so that the
184 * L2 cache settings get properly set even at resume time or if we're
185 * running U-Boot with the cache off. The kernel still needs us to
189 configure_l2_actlr();
193 relocate_wait_code();
195 /* Reconfigure secondary cores */
196 secondary_cores_configure();
199 reset_status = get_reset_status();
201 switch (reset_status) {
202 case S5P_CHECK_SLEEP:
203 actions = DO_CLOCKS | DO_WAKEUP;
205 case S5P_CHECK_DIDLE:
210 /* This is a normal boot (not a wake from sleep) */
211 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
214 if (actions & DO_POWER)
217 if (actions & DO_CLOCKS) {
219 #ifdef CONFIG_DEBUG_UART
220 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
221 !defined(CONFIG_SPL_BUILD)
222 exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
226 mem_ctrl_init(actions & DO_MEM_RESET);
230 return actions & DO_WAKEUP;