2 * Lowlevel setup for EXYNOS5 based board
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <debug_uart.h>
29 #include <asm/system.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/dmc.h>
33 #include <asm/arch/power.h>
34 #include <asm/arch/tzpc.h>
35 #include <asm/arch/periph.h>
36 #include <asm/arch/pinmux.h>
37 #include <asm/arch/system.h>
38 #include <asm/armv7.h>
39 #include "common_setup.h"
40 #include "exynos5_setup.h"
42 /* These are the things we can do during low-level init */
46 DO_MEM_RESET = 1 << 2,
51 #ifdef CONFIG_EXYNOS5420
53 /* Address for relocating helper code (Last 4 KB of IRAM) */
54 #define EXYNOS_RELOCATE_CODE_BASE (CFG_IRAM_TOP - 0x1000)
57 * Power up secondary CPUs.
59 static void secondary_cpu_start(void)
61 v7_enable_smp(EXYNOS5420_INFORM_BASE);
63 branch_bx(EXYNOS_RELOCATE_CODE_BASE);
67 * This is the entry point of hotplug-in and
70 static void low_power_start(void)
72 uint32_t val, reg_val;
74 reg_val = readl(EXYNOS5420_SPARE_BASE);
75 if (reg_val != CPU_RST_FLAG_VAL) {
76 writel(0x0, CFG_LOWPOWER_FLAG);
80 reg_val = readl(CFG_PHY_IRAM_BASE + 0x4);
81 if (reg_val != (uint32_t)&low_power_start) {
82 /* Store jump address as low_power_start if not present */
83 writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4);
88 /* Set the CPU to SVC32 mode */
91 #ifndef CONFIG_SYS_L2CACHE_OFF
92 /* Read MIDR for Primary Part Number */
100 v7_enable_l2_hazard_detect();
104 /* Invalidate L1 & TLB */
109 /* Disable MMU stuff and caches */
112 val &= ~((0x2 << 12) | 0x7);
113 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
116 /* CPU state is hotplug or reset */
117 secondary_cpu_start();
119 /* Core should not enter into WFI here */
124 * Pointer to this function is stored in iRam which is used
125 * for jump and power down of a specific core.
127 static void power_down_core(void)
129 uint32_t tmp, core_id, core_config;
131 /* Get the unique core id */
133 * Multiprocessor Affinity Register
139 core_id = (core_id >> 6) & ~3;
143 /* Set the status of the core to low */
144 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
145 core_config += EXYNOS5420_CPU_CONFIG_BASE;
146 writel(0x0, core_config);
153 * Configurations for secondary cores are inapt at this stage.
154 * Reconfigure secondary cores. Shutdown and change the status
155 * of all cores except the primary core.
157 static void secondary_cores_configure(void)
159 /* Clear secondary boot iRAM base */
160 writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));
162 /* set lowpower flag and address */
163 writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG);
164 writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR);
165 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
166 /* Store jump address for power down */
167 writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4);
169 /* Need all core power down check */
174 extern void relocate_wait_code(void);
177 int do_lowlevel_init(void)
179 uint32_t reset_status;
184 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
186 * Init L2 cache parameters here for use by boot and resume
188 * These are here instead of in v7_outer_cache_enable() so that the
189 * L2 cache settings get properly set even at resume time or if we're
190 * running U-Boot with the cache off. The kernel still needs us to
194 configure_l2_actlr();
198 relocate_wait_code();
200 /* Reconfigure secondary cores */
201 secondary_cores_configure();
204 reset_status = get_reset_status();
206 switch (reset_status) {
207 case S5P_CHECK_SLEEP:
208 actions = DO_CLOCKS | DO_WAKEUP;
210 case S5P_CHECK_DIDLE:
215 /* This is a normal boot (not a wake from sleep) */
216 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
219 if (actions & DO_POWER)
222 if (actions & DO_CLOCKS) {
224 #ifdef CONFIG_DEBUG_UART
225 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
226 !defined(CONFIG_SPL_BUILD)
227 exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
231 mem_ctrl_init(actions & DO_MEM_RESET);
235 return actions & DO_WAKEUP;