2 * Lowlevel setup for EXYNOS5 based board
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <debug_uart.h>
29 #include <asm/system.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/dmc.h>
33 #include <asm/arch/power.h>
34 #include <asm/arch/tzpc.h>
35 #include <asm/arch/periph.h>
36 #include <asm/arch/pinmux.h>
37 #include <asm/arch/system.h>
38 #include <asm/armv7.h>
39 #include "common_setup.h"
40 #include "exynos5_setup.h"
42 /* These are the things we can do during low-level init */
46 DO_MEM_RESET = 1 << 2,
51 #ifdef CONFIG_EXYNOS5420
53 * Power up secondary CPUs.
55 static void secondary_cpu_start(void)
57 v7_enable_smp(EXYNOS5420_INFORM_BASE);
59 branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
63 * This is the entry point of hotplug-in and
66 static void low_power_start(void)
68 uint32_t val, reg_val;
70 reg_val = readl(EXYNOS5420_SPARE_BASE);
71 if (reg_val != CPU_RST_FLAG_VAL) {
72 writel(0x0, CONFIG_LOWPOWER_FLAG);
76 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
77 if (reg_val != (uint32_t)&low_power_start) {
78 /* Store jump address as low_power_start if not present */
79 writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
84 /* Set the CPU to SVC32 mode */
87 #ifndef CONFIG_SYS_L2CACHE_OFF
88 /* Read MIDR for Primary Part Number */
96 v7_enable_l2_hazard_detect();
100 /* Invalidate L1 & TLB */
105 /* Disable MMU stuff and caches */
108 val &= ~((0x2 << 12) | 0x7);
109 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
112 /* CPU state is hotplug or reset */
113 secondary_cpu_start();
115 /* Core should not enter into WFI here */
120 * Pointer to this function is stored in iRam which is used
121 * for jump and power down of a specific core.
123 static void power_down_core(void)
125 uint32_t tmp, core_id, core_config;
127 /* Get the unique core id */
129 * Multiprocessor Affinity Register
135 core_id = (core_id >> 6) & ~3;
139 /* Set the status of the core to low */
140 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
141 core_config += EXYNOS5420_CPU_CONFIG_BASE;
142 writel(0x0, core_config);
149 * Configurations for secondary cores are inapt at this stage.
150 * Reconfigure secondary cores. Shutdown and change the status
151 * of all cores except the primary core.
153 static void secondary_cores_configure(void)
155 /* Clear secondary boot iRAM base */
156 writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
158 /* set lowpower flag and address */
159 writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
160 writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
161 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
162 /* Store jump address for power down */
163 writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
165 /* Need all core power down check */
170 extern void relocate_wait_code(void);
173 int do_lowlevel_init(void)
175 uint32_t reset_status;
180 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
182 * Init L2 cache parameters here for use by boot and resume
184 * These are here instead of in v7_outer_cache_enable() so that the
185 * L2 cache settings get properly set even at resume time or if we're
186 * running U-Boot with the cache off. The kernel still needs us to
190 configure_l2_actlr();
194 relocate_wait_code();
196 /* Reconfigure secondary cores */
197 secondary_cores_configure();
200 reset_status = get_reset_status();
202 switch (reset_status) {
203 case S5P_CHECK_SLEEP:
204 actions = DO_CLOCKS | DO_WAKEUP;
206 case S5P_CHECK_DIDLE:
211 /* This is a normal boot (not a wake from sleep) */
212 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
215 if (actions & DO_POWER)
218 if (actions & DO_CLOCKS) {
220 #ifdef CONFIG_DEBUG_UART
221 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
222 !defined(CONFIG_SPL_BUILD)
223 exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
227 mem_ctrl_init(actions & DO_MEM_RESET);
231 return actions & DO_WAKEUP;