1 /* linux/arch/arm/mach-exynos4/cpuidle.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/cpuidle.h>
14 #include <linux/cpu_pm.h>
16 #include <linux/export.h>
17 #include <linux/time.h>
19 #include <asm/proc-fns.h>
20 #include <asm/smp_scu.h>
21 #include <asm/suspend.h>
22 #include <asm/unified.h>
23 #include <asm/cpuidle.h>
24 #include <mach/regs-clock.h>
25 #include <mach/regs-pmu.h>
31 #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
32 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
33 (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
34 #define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
35 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
36 (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
38 #define S5P_CHECK_AFTR 0xFCBA0D10
40 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
41 struct cpuidle_driver *drv,
44 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
46 static struct cpuidle_driver exynos4_idle_driver = {
47 .name = "exynos4_idle",
49 .en_core_tk_irqen = 1,
51 [0] = ARM_CPUIDLE_WFI_STATE,
53 .enter = exynos4_enter_lowpower,
55 .target_residency = 100000,
56 .flags = CPUIDLE_FLAG_TIME_VALID,
58 .desc = "ARM power down",
62 .safe_state_index = 0,
65 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
66 static void exynos4_set_wakeupmask(void)
68 __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
71 static unsigned int g_pwr_ctrl, g_diag_reg;
73 static void save_cpu_arch_register(void)
75 /*read power control register*/
76 asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
77 /*read diagnostic register*/
78 asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
82 static void restore_cpu_arch_register(void)
84 /*write power control register*/
85 asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
86 /*write diagnostic register*/
87 asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
91 static int idle_finisher(unsigned long flags)
97 static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
98 struct cpuidle_driver *drv,
103 exynos4_set_wakeupmask();
105 /* Set value of power down register for aftr mode */
106 exynos_sys_powerdown_conf(SYS_AFTR);
108 __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
109 __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
111 save_cpu_arch_register();
113 /* Setting Central Sequence Register for power down mode */
114 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
115 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
116 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
119 cpu_suspend(0, idle_finisher);
122 if (!soc_is_exynos5250())
123 scu_enable(S5P_VA_SCU);
127 restore_cpu_arch_register();
130 * If PMU failed while entering sleep mode, WFI will be
131 * ignored by PMU and then exiting cpu_do_idle().
132 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
135 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
136 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
137 tmp |= S5P_CENTRAL_LOWPWR_CFG;
138 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
141 /* Clear wakeup state register */
142 __raw_writel(0x0, S5P_WAKEUP_STAT);
147 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
148 struct cpuidle_driver *drv,
151 int new_index = index;
153 /* This mode only can be entered when other core's are offline */
154 if (num_online_cpus() > 1)
155 new_index = drv->safe_state_index;
158 return arm_cpuidle_simple_enter(dev, drv, new_index);
160 return exynos4_enter_core0_aftr(dev, drv, new_index);
163 static void __init exynos5_core_down_clk(void)
168 * Enable arm clock down (in idle) and set arm divider
169 * ratios in WFI/WFE state.
171 tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
172 PWR_CTRL1_CORE1_DOWN_RATIO | \
173 PWR_CTRL1_DIV2_DOWN_EN | \
174 PWR_CTRL1_DIV1_DOWN_EN | \
175 PWR_CTRL1_USE_CORE1_WFE | \
176 PWR_CTRL1_USE_CORE0_WFE | \
177 PWR_CTRL1_USE_CORE1_WFI | \
178 PWR_CTRL1_USE_CORE0_WFI;
179 __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
182 * Enable arm clock up (on exiting idle). Set arm divider
183 * ratios when not in idle along with the standby duration
186 tmp = PWR_CTRL2_DIV2_UP_EN | \
187 PWR_CTRL2_DIV1_UP_EN | \
188 PWR_CTRL2_DUR_STANDBY2_VAL | \
189 PWR_CTRL2_DUR_STANDBY1_VAL | \
190 PWR_CTRL2_CORE2_UP_RATIO | \
191 PWR_CTRL2_CORE1_UP_RATIO;
192 __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
195 static int __init exynos4_init_cpuidle(void)
198 struct cpuidle_device *device;
200 if (soc_is_exynos5250())
201 exynos5_core_down_clk();
203 cpuidle_register_driver(&exynos4_idle_driver);
205 for_each_cpu(cpu_id, cpu_online_mask) {
206 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
207 device->cpu = cpu_id;
209 /* Support IDLE only */
211 device->state_count = 1;
213 if (cpuidle_register_device(device)) {
214 printk(KERN_ERR "CPUidle register device failed\n,");
221 device_initcall(exynos4_init_cpuidle);