arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <asm/proc-fns.h>
  24 #include <asm/exception.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/hardware/gic.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/regs-irq.h>
  31 #include <mach/regs-pmu.h>
  32 #include <mach/regs-gpio.h>
  33
  34 #include <plat/cpu.h>
  35 #include <plat/clock.h>
  36 #include <plat/devs.h>
  37 #include <plat/pm.h>
  38 #include <plat/sdhci.h>
  39 #include <plat/gpio-cfg.h>
  40 #include <plat/adc-core.h>
  41 #include <plat/fb-core.h>
  42 #include <plat/fimc-core.h>
  43 #include <plat/iic-core.h>
  44 #include <plat/tv-core.h>
  45 #include <plat/regs-serial.h>
  46
  47 #include "common.h"
  48
  49 static const char name_exynos4210[] = "EXYNOS4210";
  50 static const char name_exynos4212[] = "EXYNOS4212";
  51 static const char name_exynos4412[] = "EXYNOS4412";
  52
  53 static struct cpu_table cpu_ids[] __initdata = {
  54         {
  55                 .idcode         = EXYNOS4210_CPU_ID,
  56                 .idmask         = EXYNOS4_CPU_MASK,
  57                 .map_io         = exynos4_map_io,
  58                 .init_clocks    = exynos4_init_clocks,
  59                 .init_uarts     = exynos4_init_uarts,
  60                 .init           = exynos_init,
  61                 .name           = name_exynos4210,
  62         }, {
  63                 .idcode         = EXYNOS4212_CPU_ID,
  64                 .idmask         = EXYNOS4_CPU_MASK,
  65                 .map_io         = exynos4_map_io,
  66                 .init_clocks    = exynos4_init_clocks,
  67                 .init_uarts     = exynos4_init_uarts,
  68                 .init           = exynos_init,
  69                 .name           = name_exynos4212,
  70         }, {
  71                 .idcode         = EXYNOS4412_CPU_ID,
  72                 .idmask         = EXYNOS4_CPU_MASK,
  73                 .map_io         = exynos4_map_io,
  74                 .init_clocks    = exynos4_init_clocks,
  75                 .init_uarts     = exynos4_init_uarts,
  76                 .init           = exynos_init,
  77                 .name           = name_exynos4412,
  78         },
  79 };
  80
  81 /* Initial IO mappings */
  82
  83 static struct map_desc exynos_iodesc[] __initdata = {
  84         {
  85                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  86                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S3C_VA_SYS,
  91                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  92                 .length         = SZ_64K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S3C_VA_TIMER,
  96                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  97                 .length         = SZ_16K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 101                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_SROMC,
 106                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 111                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)S5P_VA_PMU,
 116                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 117                 .length         = SZ_64K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 121                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 127                 .length         = SZ_64K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 132                 .length         = SZ_64K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S3C_VA_UART,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 137                 .length         = SZ_512K,
 138                 .type           = MT_DEVICE,
 139         },
 140 };
 141
 142 static struct map_desc exynos4_iodesc[] __initdata = {
 143         {
 144                 .virtual        = (unsigned long)S5P_VA_CMU,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 146                 .length         = SZ_128K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 151                 .length         = SZ_8K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_L2CC,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 156                 .length         = SZ_4K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_GPIO1,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
 161                 .length         = SZ_4K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_GPIO2,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
 166                 .length         = SZ_4K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_GPIO3,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
 171                 .length         = SZ_256,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_DMC0,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 176                 .length         = SZ_4K,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 181                 .length         = SZ_4K,
 182                 .type           = MT_DEVICE,
 183         },
 184 };
 185
 186 static struct map_desc exynos4_iodesc0[] __initdata = {
 187         {
 188                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 189                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 190                 .length         = SZ_4K,
 191                 .type           = MT_DEVICE,
 192         },
 193 };
 194
 195 static struct map_desc exynos4_iodesc1[] __initdata = {
 196         {
 197                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 199                 .length         = SZ_4K,
 200                 .type           = MT_DEVICE,
 201         },
 202 };
 203
 204 void exynos4_restart(char mode, const char *cmd)
 205 {
 206         __raw_writel(0x1, S5P_SWRESET);
 207 }
 208
 209 /*
 210  * exynos_map_io
 211  *
 212  * register the standard cpu IO areas
 213  */
 214
 215 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 216 {
 217         /* initialize the io descriptors we need for initialization */
 218         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 219         if (mach_desc)
 220                 iotable_init(mach_desc, size);
 221
 222         /* detect cpu id and rev. */
 223         s5p_init_cpu(S5P_VA_CHIPID);
 224
 225         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 226 }
 227
 228 void __init exynos4_map_io(void)
 229 {
 230         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 231
 232         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 233                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 234         else
 235                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 236
 237         /* initialize device information early */
 238         exynos4_default_sdhci0();
 239         exynos4_default_sdhci1();
 240         exynos4_default_sdhci2();
 241         exynos4_default_sdhci3();
 242
 243         s3c_adc_setname("samsung-adc-v3");
 244
 245         s3c_fimc_setname(0, "exynos4-fimc");
 246         s3c_fimc_setname(1, "exynos4-fimc");
 247         s3c_fimc_setname(2, "exynos4-fimc");
 248         s3c_fimc_setname(3, "exynos4-fimc");
 249
 250         /* The I2C bus controllers are directly compatible with s3c2440 */
 251         s3c_i2c0_setname("s3c2440-i2c");
 252         s3c_i2c1_setname("s3c2440-i2c");
 253         s3c_i2c2_setname("s3c2440-i2c");
 254
 255         s5p_fb_setname(0, "exynos4-fb");
 256         s5p_hdmi_setname("exynos4-hdmi");
 257 }
 258
 259 void __init exynos4_init_clocks(int xtal)
 260 {
 261         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 262
 263         s3c24xx_register_baseclocks(xtal);
 264         s5p_register_clocks(xtal);
 265
 266         if (soc_is_exynos4210())
 267                 exynos4210_register_clocks();
 268         else if (soc_is_exynos4212() || soc_is_exynos4412())
 269                 exynos4212_register_clocks();
 270
 271         exynos4_register_clocks();
 272         exynos4_setup_clocks();
 273 }
 274
 275 #define COMBINER_ENABLE_SET     0x0
 276 #define COMBINER_ENABLE_CLEAR   0x4
 277 #define COMBINER_INT_STATUS     0xC
 278
 279 static DEFINE_SPINLOCK(irq_controller_lock);
 280
 281 struct combiner_chip_data {
 282         unsigned int irq_offset;
 283         unsigned int irq_mask;
 284         void __iomem *base;
 285 };
 286
 287 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 288
 289 static inline void __iomem *combiner_base(struct irq_data *data)
 290 {
 291         struct combiner_chip_data *combiner_data =
 292                 irq_data_get_irq_chip_data(data);
 293
 294         return combiner_data->base;
 295 }
 296
 297 static void combiner_mask_irq(struct irq_data *data)
 298 {
 299         u32 mask = 1 << (data->irq % 32);
 300
 301         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 302 }
 303
 304 static void combiner_unmask_irq(struct irq_data *data)
 305 {
 306         u32 mask = 1 << (data->irq % 32);
 307
 308         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 309 }
 310
 311 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 312 {
 313         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 314         struct irq_chip *chip = irq_get_chip(irq);
 315         unsigned int cascade_irq, combiner_irq;
 316         unsigned long status;
 317
 318         chained_irq_enter(chip, desc);
 319
 320         spin_lock(&irq_controller_lock);
 321         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 322         spin_unlock(&irq_controller_lock);
 323         status &= chip_data->irq_mask;
 324
 325         if (status == 0)
 326                 goto out;
 327
 328         combiner_irq = __ffs(status);
 329
 330         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 331         if (unlikely(cascade_irq >= NR_IRQS))
 332                 do_bad_IRQ(cascade_irq, desc);
 333         else
 334                 generic_handle_irq(cascade_irq);
 335
 336  out:
 337         chained_irq_exit(chip, desc);
 338 }
 339
 340 static struct irq_chip combiner_chip = {
 341         .name           = "COMBINER",
 342         .irq_mask       = combiner_mask_irq,
 343         .irq_unmask     = combiner_unmask_irq,
 344 };
 345
 346 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 347 {
 348         if (combiner_nr >= MAX_COMBINER_NR)
 349                 BUG();
 350         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 351                 BUG();
 352         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 353 }
 354
 355 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 356                           unsigned int irq_start)
 357 {
 358         unsigned int i;
 359
 360         if (combiner_nr >= MAX_COMBINER_NR)
 361                 BUG();
 362
 363         combiner_data[combiner_nr].base = base;
 364         combiner_data[combiner_nr].irq_offset = irq_start;
 365         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 366
 367         /* Disable all interrupts */
 368
 369         __raw_writel(combiner_data[combiner_nr].irq_mask,
 370                      base + COMBINER_ENABLE_CLEAR);
 371
 372         /* Setup the Linux IRQ subsystem */
 373
 374         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
 375                                 + MAX_IRQ_IN_COMBINER; i++) {
 376                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
 377                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
 378                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 379         }
 380 }
 381
 382 #ifdef CONFIG_OF
 383 static const struct of_device_id exynos4_dt_irq_match[] = {
 384         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 385         {},
 386 };
 387 #endif
 388
 389 void __init exynos4_init_irq(void)
 390 {
 391         int irq;
 392         unsigned int gic_bank_offset;
 393
 394         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 395
 396         if (!of_have_populated_dt())
 397                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 398 #ifdef CONFIG_OF
 399         else
 400                 of_irq_init(exynos4_dt_irq_match);
 401 #endif
 402
 403         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 404
 405                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 406                                 COMBINER_IRQ(irq, 0));
 407                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 408         }
 409
 410         /*
 411          * The parameters of s5p_init_irq() are for VIC init.
 412          * Theses parameters should be NULL and 0 because EXYNOS4
 413          * uses GIC instead of VIC.
 414          */
 415         s5p_init_irq(NULL, 0);
 416 }
 417
 418 struct bus_type exynos4_subsys = {
 419         .name           = "exynos4-core",
 420         .dev_name       = "exynos4-core",
 421 };
 422
 423 static struct device exynos4_dev = {
 424         .bus    = &exynos4_subsys,
 425 };
 426
 427 static int __init exynos4_core_init(void)
 428 {
 429         return subsys_system_register(&exynos4_subsys, NULL);
 430 }
 431 core_initcall(exynos4_core_init);
 432
 433 #ifdef CONFIG_CACHE_L2X0
 434 static int __init exynos4_l2x0_cache_init(void)
 435 {
 436         /* TAG, Data Latency Control: 2cycle */
 437         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 438
 439         if (soc_is_exynos4210())
 440                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 441         else if (soc_is_exynos4212() || soc_is_exynos4412())
 442                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 443
 444         /* L2X0 Prefetch Control */
 445         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 446
 447         /* L2X0 Power Control */
 448         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 449                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 450
 451         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 452
 453         return 0;
 454 }
 455
 456 early_initcall(exynos4_l2x0_cache_init);
 457 #endif
 458
 459 int __init exynos_init(void)
 460 {
 461         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 462         return device_register(&exynos4_dev);
 463 }
 464
 465 /* uart registration process */
 466
 467 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 468 {
 469         struct s3c2410_uartcfg *tcfg = cfg;
 470         u32 ucnt;
 471
 472         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 473                 tcfg->has_fracval = 1;
 474
 475         s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
 476 }
 477
 478 static DEFINE_SPINLOCK(eint_lock);
 479
 480 static unsigned int eint0_15_data[16];
 481
 482 static unsigned int exynos4_get_irq_nr(unsigned int number)
 483 {
 484         u32 ret = 0;
 485
 486         switch (number) {
 487         case 0 ... 3:
 488                 ret = (number + IRQ_EINT0);
 489                 break;
 490         case 4 ... 7:
 491                 ret = (number + (IRQ_EINT4 - 4));
 492                 break;
 493         case 8 ... 15:
 494                 ret = (number + (IRQ_EINT8 - 8));
 495                 break;
 496         default:
 497                 printk(KERN_ERR "number available : %d\n", number);
 498         }
 499
 500         return ret;
 501 }
 502
 503 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 504 {
 505         u32 mask;
 506
 507         spin_lock(&eint_lock);
 508         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 509         mask |= eint_irq_to_bit(data->irq);
 510         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 511         spin_unlock(&eint_lock);
 512 }
 513
 514 static void exynos4_irq_eint_unmask(struct irq_data *data)
 515 {
 516         u32 mask;
 517
 518         spin_lock(&eint_lock);
 519         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 520         mask &= ~(eint_irq_to_bit(data->irq));
 521         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 522         spin_unlock(&eint_lock);
 523 }
 524
 525 static inline void exynos4_irq_eint_ack(struct irq_data *data)
 526 {
 527         __raw_writel(eint_irq_to_bit(data->irq),
 528                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 529 }
 530
 531 static void exynos4_irq_eint_maskack(struct irq_data *data)
 532 {
 533         exynos4_irq_eint_mask(data);
 534         exynos4_irq_eint_ack(data);
 535 }
 536
 537 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 538 {
 539         int offs = EINT_OFFSET(data->irq);
 540         int shift;
 541         u32 ctrl, mask;
 542         u32 newvalue = 0;
 543
 544         switch (type) {
 545         case IRQ_TYPE_EDGE_RISING:
 546                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 547                 break;
 548
 549         case IRQ_TYPE_EDGE_FALLING:
 550                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 551                 break;
 552
 553         case IRQ_TYPE_EDGE_BOTH:
 554                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 555                 break;
 556
 557         case IRQ_TYPE_LEVEL_LOW:
 558                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 559                 break;
 560
 561         case IRQ_TYPE_LEVEL_HIGH:
 562                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 563                 break;
 564
 565         default:
 566                 printk(KERN_ERR "No such irq type %d", type);
 567                 return -EINVAL;
 568         }
 569
 570         shift = (offs & 0x7) * 4;
 571         mask = 0x7 << shift;
 572
 573         spin_lock(&eint_lock);
 574         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
 575         ctrl &= ~mask;
 576         ctrl |= newvalue << shift;
 577         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
 578         spin_unlock(&eint_lock);
 579
 580         switch (offs) {
 581         case 0 ... 7:
 582                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
 583                 break;
 584         case 8 ... 15:
 585                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
 586                 break;
 587         case 16 ... 23:
 588                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
 589                 break;
 590         case 24 ... 31:
 591                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
 592                 break;
 593         default:
 594                 printk(KERN_ERR "No such irq number %d", offs);
 595         }
 596
 597         return 0;
 598 }
 599
 600 static struct irq_chip exynos4_irq_eint = {
 601         .name           = "exynos4-eint",
 602         .irq_mask       = exynos4_irq_eint_mask,
 603         .irq_unmask     = exynos4_irq_eint_unmask,
 604         .irq_mask_ack   = exynos4_irq_eint_maskack,
 605         .irq_ack        = exynos4_irq_eint_ack,
 606         .irq_set_type   = exynos4_irq_eint_set_type,
 607 #ifdef CONFIG_PM
 608         .irq_set_wake   = s3c_irqext_wake,
 609 #endif
 610 };
 611
 612 /*
 613  * exynos4_irq_demux_eint
 614  *
 615  * This function demuxes the IRQ from from EINTs 16 to 31.
 616  * It is designed to be inlined into the specific handler
 617  * s5p_irq_demux_eintX_Y.
 618  *
 619  * Each EINT pend/mask registers handle eight of them.
 620  */
 621 static inline void exynos4_irq_demux_eint(unsigned int start)
 622 {
 623         unsigned int irq;
 624
 625         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
 626         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
 627
 628         status &= ~mask;
 629         status &= 0xff;
 630
 631         while (status) {
 632                 irq = fls(status) - 1;
 633                 generic_handle_irq(irq + start);
 634                 status &= ~(1 << irq);
 635         }
 636 }
 637
 638 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 639 {
 640         struct irq_chip *chip = irq_get_chip(irq);
 641         chained_irq_enter(chip, desc);
 642         exynos4_irq_demux_eint(IRQ_EINT(16));
 643         exynos4_irq_demux_eint(IRQ_EINT(24));
 644         chained_irq_exit(chip, desc);
 645 }
 646
 647 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 648 {
 649         u32 *irq_data = irq_get_handler_data(irq);
 650         struct irq_chip *chip = irq_get_chip(irq);
 651
 652         chained_irq_enter(chip, desc);
 653         chip->irq_mask(&desc->irq_data);
 654
 655         if (chip->irq_ack)
 656                 chip->irq_ack(&desc->irq_data);
 657
 658         generic_handle_irq(*irq_data);
 659
 660         chip->irq_unmask(&desc->irq_data);
 661         chained_irq_exit(chip, desc);
 662 }
 663
 664 int __init exynos4_init_irq_eint(void)
 665 {
 666         int irq;
 667
 668         for (irq = 0 ; irq <= 31 ; irq++) {
 669                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 670                                          handle_level_irq);
 671                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 672         }
 673
 674         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 675
 676         for (irq = 0 ; irq <= 15 ; irq++) {
 677                 eint0_15_data[irq] = IRQ_EINT(irq);
 678
 679                 irq_set_handler_data(exynos4_get_irq_nr(irq),
 680                                      &eint0_15_data[irq]);
 681                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
 682                                         exynos4_irq_eint0_15);
 683         }
 684
 685         return 0;
 686 }
 687 arch_initcall(exynos4_init_irq_eint);