arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
  34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
  35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
  36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
  37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
  38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
  39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
  40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
  41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
  42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
  43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
  44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
  45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
  46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
  47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
  48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
  49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
  50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
  51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
  52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
  53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
  54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
  60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
  61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
  62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
  63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
  64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
  65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
  66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
  67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
  68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
  69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
  70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
  71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
  72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
  73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
  74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
  75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
  76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
  77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
  78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
  79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
  80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
  81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
  82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
  83 };
  84 #endif
  85
  86 static struct clk exynos5_clk_sclk_dptxphy = {
  87         .name           = "sclk_dptx",
  88 };
  89
  90 static struct clk exynos5_clk_sclk_hdmi24m = {
  91         .name           = "sclk_hdmi24m",
  92         .rate           = 24000000,
  93 };
  94
  95 static struct clk exynos5_clk_sclk_hdmi27m = {
  96         .name           = "sclk_hdmi27m",
  97         .rate           = 27000000,
  98 };
  99
 100 static struct clk exynos5_clk_sclk_hdmiphy = {
 101         .name           = "sclk_hdmiphy",
 102 };
 103
 104 static struct clk exynos5_clk_sclk_usbphy = {
 105         .name           = "sclk_usbphy",
 106         .rate           = 48000000,
 107 };
 108
 109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
 112 }
 113
 114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
 117 }
 118
 119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
 122 }
 123
 124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
 127 }
 128
 129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 132 }
 133
 134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
 137 }
 138
 139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
 142 }
 143
 144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
 147 }
 148
 149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
 152 }
 153
 154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 157 }
 158
 159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 162 }
 163
 164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 167 }
 168
 169 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 172 }
 173
 174 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 177 }
 178
 179 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 182 }
 183
 184 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 187 }
 188
 189 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 190 {
 191         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 192 }
 193
 194 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 195 {
 196         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 197 }
 198
 199 /* Core list of CMU_CPU side */
 200
 201 static struct clksrc_clk exynos5_clk_mout_apll = {
 202         .clk    = {
 203                 .name           = "mout_apll",
 204         },
 205         .sources = &clk_src_apll,
 206         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 207 };
 208
 209 static struct clksrc_clk exynos5_clk_sclk_apll = {
 210         .clk    = {
 211                 .name           = "sclk_apll",
 212                 .parent         = &exynos5_clk_mout_apll.clk,
 213         },
 214         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 215 };
 216
 217 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 218         .clk    = {
 219                 .name           = "mout_bpll_fout",
 220         },
 221         .sources = &clk_src_bpll_fout,
 222         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 223 };
 224
 225 static struct clk *exynos5_clk_src_bpll_list[] = {
 226         [0] = &clk_fin_bpll,
 227         [1] = &exynos5_clk_mout_bpll_fout.clk,
 228 };
 229
 230 static struct clksrc_sources exynos5_clk_src_bpll = {
 231         .sources        = exynos5_clk_src_bpll_list,
 232         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 233 };
 234
 235 static struct clksrc_clk exynos5_clk_mout_bpll = {
 236         .clk    = {
 237                 .name           = "mout_bpll",
 238         },
 239         .sources = &exynos5_clk_src_bpll,
 240         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 241 };
 242
 243 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 244         [0] = &clk_fin_mpll,
 245         [1] = &exynos5_clk_mout_bpll.clk,
 246 };
 247
 248 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 249         .sources        = exynos5_clk_src_bpll_user_list,
 250         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 251 };
 252
 253 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 254         .clk    = {
 255                 .name           = "mout_bpll_user",
 256         },
 257         .sources = &exynos5_clk_src_bpll_user,
 258         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 259 };
 260
 261 static struct clksrc_clk exynos5_clk_mout_cpll = {
 262         .clk    = {
 263                 .name           = "mout_cpll",
 264         },
 265         .sources = &clk_src_cpll,
 266         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos5_clk_mout_epll = {
 270         .clk    = {
 271                 .name           = "mout_epll",
 272         },
 273         .sources = &clk_src_epll,
 274         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 275 };
 276
 277 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 278         .clk    = {
 279                 .name           = "mout_mpll_fout",
 280         },
 281         .sources = &clk_src_mpll_fout,
 282         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 283 };
 284
 285 static struct clk *exynos5_clk_src_mpll_list[] = {
 286         [0] = &clk_fin_mpll,
 287         [1] = &exynos5_clk_mout_mpll_fout.clk,
 288 };
 289
 290 static struct clksrc_sources exynos5_clk_src_mpll = {
 291         .sources        = exynos5_clk_src_mpll_list,
 292         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 293 };
 294
 295 struct clksrc_clk exynos5_clk_mout_mpll = {
 296         .clk = {
 297                 .name           = "mout_mpll",
 298         },
 299         .sources = &exynos5_clk_src_mpll,
 300         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 301 };
 302
 303 static struct clk *exynos_clkset_vpllsrc_list[] = {
 304         [0] = &clk_fin_vpll,
 305         [1] = &exynos5_clk_sclk_hdmi27m,
 306 };
 307
 308 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 309         .sources        = exynos_clkset_vpllsrc_list,
 310         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 311 };
 312
 313 static struct clksrc_clk exynos5_clk_vpllsrc = {
 314         .clk    = {
 315                 .name           = "vpll_src",
 316                 .enable         = exynos5_clksrc_mask_top_ctrl,
 317                 .ctrlbit        = (1 << 0),
 318         },
 319         .sources = &exynos5_clkset_vpllsrc,
 320         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 321 };
 322
 323 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 324         [0] = &exynos5_clk_vpllsrc.clk,
 325         [1] = &clk_fout_vpll,
 326 };
 327
 328 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 329         .sources        = exynos5_clkset_sclk_vpll_list,
 330         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 331 };
 332
 333 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 334         .clk    = {
 335                 .name           = "sclk_vpll",
 336         },
 337         .sources = &exynos5_clkset_sclk_vpll,
 338         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 339 };
 340
 341 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 342         .clk    = {
 343                 .name           = "sclk_pixel",
 344                 .parent         = &exynos5_clk_sclk_vpll.clk,
 345         },
 346         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 347 };
 348
 349 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 350         [0] = &exynos5_clk_sclk_pixel.clk,
 351         [1] = &exynos5_clk_sclk_hdmiphy,
 352 };
 353
 354 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 355         .sources        = exynos5_clkset_sclk_hdmi_list,
 356         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 357 };
 358
 359 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 360         .clk    = {
 361                 .name           = "sclk_hdmi",
 362                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 363                 .ctrlbit        = (1 << 20),
 364         },
 365         .sources = &exynos5_clkset_sclk_hdmi,
 366         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 367 };
 368
 369 static struct clksrc_clk *exynos5_sclk_tv[] = {
 370         &exynos5_clk_sclk_pixel,
 371         &exynos5_clk_sclk_hdmi,
 372 };
 373
 374 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 375         [0] = &clk_fin_mpll,
 376         [1] = &exynos5_clk_mout_mpll.clk,
 377 };
 378
 379 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 380         .sources        = exynos5_clk_src_mpll_user_list,
 381         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 382 };
 383
 384 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 385         .clk    = {
 386                 .name           = "mout_mpll_user",
 387         },
 388         .sources = &exynos5_clk_src_mpll_user,
 389         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 390 };
 391
 392 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 393         [0] = &exynos5_clk_mout_apll.clk,
 394         [1] = &exynos5_clk_mout_mpll.clk,
 395 };
 396
 397 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 398         .sources        = exynos5_clkset_mout_cpu_list,
 399         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 400 };
 401
 402 static struct clksrc_clk exynos5_clk_mout_cpu = {
 403         .clk    = {
 404                 .name           = "mout_cpu",
 405         },
 406         .sources = &exynos5_clkset_mout_cpu,
 407         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 408 };
 409
 410 static struct clksrc_clk exynos5_clk_dout_armclk = {
 411         .clk    = {
 412                 .name           = "dout_armclk",
 413                 .parent         = &exynos5_clk_mout_cpu.clk,
 414         },
 415         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 416 };
 417
 418 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 419         .clk    = {
 420                 .name           = "dout_arm2clk",
 421                 .parent         = &exynos5_clk_dout_armclk.clk,
 422         },
 423         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 424 };
 425
 426 static struct clk exynos5_clk_armclk = {
 427         .name           = "armclk",
 428         .parent         = &exynos5_clk_dout_arm2clk.clk,
 429 };
 430
 431 /* Core list of CMU_CDREX side */
 432
 433 static struct clk *exynos5_clkset_cdrex_list[] = {
 434         [0] = &exynos5_clk_mout_mpll.clk,
 435         [1] = &exynos5_clk_mout_bpll.clk,
 436 };
 437
 438 static struct clksrc_sources exynos5_clkset_cdrex = {
 439         .sources        = exynos5_clkset_cdrex_list,
 440         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 441 };
 442
 443 static struct clksrc_clk exynos5_clk_cdrex = {
 444         .clk    = {
 445                 .name           = "clk_cdrex",
 446         },
 447         .sources = &exynos5_clkset_cdrex,
 448         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 449         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 450 };
 451
 452 static struct clksrc_clk exynos5_clk_aclk_acp = {
 453         .clk    = {
 454                 .name           = "aclk_acp",
 455                 .parent         = &exynos5_clk_mout_mpll.clk,
 456         },
 457         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 458 };
 459
 460 static struct clksrc_clk exynos5_clk_pclk_acp = {
 461         .clk    = {
 462                 .name           = "pclk_acp",
 463                 .parent         = &exynos5_clk_aclk_acp.clk,
 464         },
 465         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 466 };
 467
 468 /* Core list of CMU_TOP side */
 469
 470 struct clk *exynos5_clkset_aclk_top_list[] = {
 471         [0] = &exynos5_clk_mout_mpll_user.clk,
 472         [1] = &exynos5_clk_mout_bpll_user.clk,
 473 };
 474
 475 struct clksrc_sources exynos5_clkset_aclk = {
 476         .sources        = exynos5_clkset_aclk_top_list,
 477         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 478 };
 479
 480 static struct clksrc_clk exynos5_clk_aclk_400 = {
 481         .clk    = {
 482                 .name           = "aclk_400",
 483         },
 484         .sources = &exynos5_clkset_aclk,
 485         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 486         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 487 };
 488
 489 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 490         [0] = &exynos5_clk_mout_cpll.clk,
 491         [1] = &exynos5_clk_mout_mpll_user.clk,
 492 };
 493
 494 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 495         .sources        = exynos5_clkset_aclk_333_166_list,
 496         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 497 };
 498
 499 static struct clksrc_clk exynos5_clk_aclk_333 = {
 500         .clk    = {
 501                 .name           = "aclk_333",
 502         },
 503         .sources = &exynos5_clkset_aclk_333_166,
 504         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 505         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 506 };
 507
 508 static struct clksrc_clk exynos5_clk_aclk_166 = {
 509         .clk    = {
 510                 .name           = "aclk_166",
 511         },
 512         .sources = &exynos5_clkset_aclk_333_166,
 513         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 514         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 515 };
 516
 517 static struct clksrc_clk exynos5_clk_aclk_266 = {
 518         .clk    = {
 519                 .name           = "aclk_266",
 520                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 521         },
 522         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 523 };
 524
 525 static struct clksrc_clk exynos5_clk_aclk_200 = {
 526         .clk    = {
 527                 .name           = "aclk_200",
 528         },
 529         .sources = &exynos5_clkset_aclk,
 530         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 531         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 532 };
 533
 534 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 535         .clk    = {
 536                 .name           = "aclk_66_pre",
 537                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 538         },
 539         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 540 };
 541
 542 static struct clksrc_clk exynos5_clk_aclk_66 = {
 543         .clk    = {
 544                 .name           = "aclk_66",
 545                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 546         },
 547         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 548 };
 549
 550 static struct clk exynos5_init_clocks_off[] = {
 551         {
 552                 .name           = "timers",
 553                 .parent         = &exynos5_clk_aclk_66.clk,
 554                 .enable         = exynos5_clk_ip_peric_ctrl,
 555                 .ctrlbit        = (1 << 24),
 556         }, {
 557                 .name           = "rtc",
 558                 .parent         = &exynos5_clk_aclk_66.clk,
 559                 .enable         = exynos5_clk_ip_peris_ctrl,
 560                 .ctrlbit        = (1 << 20),
 561         }, {
 562                 .name           = "watchdog",
 563                 .parent         = &exynos5_clk_aclk_66.clk,
 564                 .enable         = exynos5_clk_ip_peris_ctrl,
 565                 .ctrlbit        = (1 << 19),
 566         }, {
 567                 .name           = "hsmmc",
 568                 .devname        = "exynos4-sdhci.0",
 569                 .parent         = &exynos5_clk_aclk_200.clk,
 570                 .enable         = exynos5_clk_ip_fsys_ctrl,
 571                 .ctrlbit        = (1 << 12),
 572         }, {
 573                 .name           = "hsmmc",
 574                 .devname        = "exynos4-sdhci.1",
 575                 .parent         = &exynos5_clk_aclk_200.clk,
 576                 .enable         = exynos5_clk_ip_fsys_ctrl,
 577                 .ctrlbit        = (1 << 13),
 578         }, {
 579                 .name           = "hsmmc",
 580                 .devname        = "exynos4-sdhci.2",
 581                 .parent         = &exynos5_clk_aclk_200.clk,
 582                 .enable         = exynos5_clk_ip_fsys_ctrl,
 583                 .ctrlbit        = (1 << 14),
 584         }, {
 585                 .name           = "hsmmc",
 586                 .devname        = "exynos4-sdhci.3",
 587                 .parent         = &exynos5_clk_aclk_200.clk,
 588                 .enable         = exynos5_clk_ip_fsys_ctrl,
 589                 .ctrlbit        = (1 << 15),
 590         }, {
 591                 .name           = "dwmci",
 592                 .parent         = &exynos5_clk_aclk_200.clk,
 593                 .enable         = exynos5_clk_ip_fsys_ctrl,
 594                 .ctrlbit        = (1 << 16),
 595         }, {
 596                 .name           = "sata",
 597                 .devname        = "ahci",
 598                 .enable         = exynos5_clk_ip_fsys_ctrl,
 599                 .ctrlbit        = (1 << 6),
 600         }, {
 601                 .name           = "sata_phy",
 602                 .enable         = exynos5_clk_ip_fsys_ctrl,
 603                 .ctrlbit        = (1 << 24),
 604         }, {
 605                 .name           = "sata_phy_i2c",
 606                 .enable         = exynos5_clk_ip_fsys_ctrl,
 607                 .ctrlbit        = (1 << 25),
 608         }, {
 609                 .name           = "mfc",
 610                 .devname        = "s5p-mfc",
 611                 .enable         = exynos5_clk_ip_mfc_ctrl,
 612                 .ctrlbit        = (1 << 0),
 613         }, {
 614                 .name           = "hdmi",
 615                 .devname        = "exynos4-hdmi",
 616                 .enable         = exynos5_clk_ip_disp1_ctrl,
 617                 .ctrlbit        = (1 << 6),
 618         }, {
 619                 .name           = "mixer",
 620                 .devname        = "s5p-mixer",
 621                 .enable         = exynos5_clk_ip_disp1_ctrl,
 622                 .ctrlbit        = (1 << 5),
 623         }, {
 624                 .name           = "jpeg",
 625                 .enable         = exynos5_clk_ip_gen_ctrl,
 626                 .ctrlbit        = (1 << 2),
 627         }, {
 628                 .name           = "dsim0",
 629                 .enable         = exynos5_clk_ip_disp1_ctrl,
 630                 .ctrlbit        = (1 << 3),
 631         }, {
 632                 .name           = "iis",
 633                 .devname        = "samsung-i2s.1",
 634                 .enable         = exynos5_clk_ip_peric_ctrl,
 635                 .ctrlbit        = (1 << 20),
 636         }, {
 637                 .name           = "iis",
 638                 .devname        = "samsung-i2s.2",
 639                 .enable         = exynos5_clk_ip_peric_ctrl,
 640                 .ctrlbit        = (1 << 21),
 641         }, {
 642                 .name           = "pcm",
 643                 .devname        = "samsung-pcm.1",
 644                 .enable         = exynos5_clk_ip_peric_ctrl,
 645                 .ctrlbit        = (1 << 22),
 646         }, {
 647                 .name           = "pcm",
 648                 .devname        = "samsung-pcm.2",
 649                 .enable         = exynos5_clk_ip_peric_ctrl,
 650                 .ctrlbit        = (1 << 23),
 651         }, {
 652                 .name           = "spdif",
 653                 .devname        = "samsung-spdif",
 654                 .enable         = exynos5_clk_ip_peric_ctrl,
 655                 .ctrlbit        = (1 << 26),
 656         }, {
 657                 .name           = "ac97",
 658                 .devname        = "samsung-ac97",
 659                 .enable         = exynos5_clk_ip_peric_ctrl,
 660                 .ctrlbit        = (1 << 27),
 661         }, {
 662                 .name           = "usbhost",
 663                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 664                 .ctrlbit        = (1 << 18),
 665         }, {
 666                 .name           = "usbotg",
 667                 .enable         = exynos5_clk_ip_fsys_ctrl,
 668                 .ctrlbit        = (1 << 7),
 669         }, {
 670                 .name           = "nfcon",
 671                 .enable         = exynos5_clk_ip_fsys_ctrl,
 672                 .ctrlbit        = (1 << 22),
 673         }, {
 674                 .name           = "iop",
 675                 .enable         = exynos5_clk_ip_fsys_ctrl,
 676                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 677         }, {
 678                 .name           = "core_iop",
 679                 .enable         = exynos5_clk_ip_core_ctrl,
 680                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 681         }, {
 682                 .name           = "mcu_iop",
 683                 .enable         = exynos5_clk_ip_fsys_ctrl,
 684                 .ctrlbit        = (1 << 0),
 685         }, {
 686                 .name           = "i2c",
 687                 .devname        = "s3c2440-i2c.0",
 688                 .parent         = &exynos5_clk_aclk_66.clk,
 689                 .enable         = exynos5_clk_ip_peric_ctrl,
 690                 .ctrlbit        = (1 << 6),
 691         }, {
 692                 .name           = "i2c",
 693                 .devname        = "s3c2440-i2c.1",
 694                 .parent         = &exynos5_clk_aclk_66.clk,
 695                 .enable         = exynos5_clk_ip_peric_ctrl,
 696                 .ctrlbit        = (1 << 7),
 697         }, {
 698                 .name           = "i2c",
 699                 .devname        = "s3c2440-i2c.2",
 700                 .parent         = &exynos5_clk_aclk_66.clk,
 701                 .enable         = exynos5_clk_ip_peric_ctrl,
 702                 .ctrlbit        = (1 << 8),
 703         }, {
 704                 .name           = "i2c",
 705                 .devname        = "s3c2440-i2c.3",
 706                 .parent         = &exynos5_clk_aclk_66.clk,
 707                 .enable         = exynos5_clk_ip_peric_ctrl,
 708                 .ctrlbit        = (1 << 9),
 709         }, {
 710                 .name           = "i2c",
 711                 .devname        = "s3c2440-i2c.4",
 712                 .parent         = &exynos5_clk_aclk_66.clk,
 713                 .enable         = exynos5_clk_ip_peric_ctrl,
 714                 .ctrlbit        = (1 << 10),
 715         }, {
 716                 .name           = "i2c",
 717                 .devname        = "s3c2440-i2c.5",
 718                 .parent         = &exynos5_clk_aclk_66.clk,
 719                 .enable         = exynos5_clk_ip_peric_ctrl,
 720                 .ctrlbit        = (1 << 11),
 721         }, {
 722                 .name           = "i2c",
 723                 .devname        = "s3c2440-i2c.6",
 724                 .parent         = &exynos5_clk_aclk_66.clk,
 725                 .enable         = exynos5_clk_ip_peric_ctrl,
 726                 .ctrlbit        = (1 << 12),
 727         }, {
 728                 .name           = "i2c",
 729                 .devname        = "s3c2440-i2c.7",
 730                 .parent         = &exynos5_clk_aclk_66.clk,
 731                 .enable         = exynos5_clk_ip_peric_ctrl,
 732                 .ctrlbit        = (1 << 13),
 733         }, {
 734                 .name           = "i2c",
 735                 .devname        = "s3c2440-hdmiphy-i2c",
 736                 .parent         = &exynos5_clk_aclk_66.clk,
 737                 .enable         = exynos5_clk_ip_peric_ctrl,
 738                 .ctrlbit        = (1 << 14),
 739         }, {
 740                 .name           = "spi",
 741                 .devname        = "exynos4210-spi.0",
 742                 .parent         = &exynos5_clk_aclk_66.clk,
 743                 .enable         = exynos5_clk_ip_peric_ctrl,
 744                 .ctrlbit        = (1 << 16),
 745         }, {
 746                 .name           = "spi",
 747                 .devname        = "exynos4210-spi.1",
 748                 .parent         = &exynos5_clk_aclk_66.clk,
 749                 .enable         = exynos5_clk_ip_peric_ctrl,
 750                 .ctrlbit        = (1 << 17),
 751         }, {
 752                 .name           = "spi",
 753                 .devname        = "exynos4210-spi.2",
 754                 .parent         = &exynos5_clk_aclk_66.clk,
 755                 .enable         = exynos5_clk_ip_peric_ctrl,
 756                 .ctrlbit        = (1 << 18),
 757         }, {
 758                 .name           = SYSMMU_CLOCK_NAME,
 759                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 760                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 761                 .ctrlbit        = (1 << 1),
 762         }, {
 763                 .name           = SYSMMU_CLOCK_NAME,
 764                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 765                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 766                 .ctrlbit        = (1 << 2),
 767         }, {
 768                 .name           = SYSMMU_CLOCK_NAME,
 769                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 770                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 771                 .ctrlbit        = (1 << 9)
 772         }, {
 773                 .name           = SYSMMU_CLOCK_NAME,
 774                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 775                 .enable         = &exynos5_clk_ip_gen_ctrl,
 776                 .ctrlbit        = (1 << 7),
 777         }, {
 778                 .name           = SYSMMU_CLOCK_NAME,
 779                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 780                 .enable         = &exynos5_clk_ip_gen_ctrl,
 781                 .ctrlbit        = (1 << 6)
 782         }, {
 783                 .name           = SYSMMU_CLOCK_NAME,
 784                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 785                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 786                 .ctrlbit        = (1 << 7),
 787         }, {
 788                 .name           = SYSMMU_CLOCK_NAME,
 789                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 790                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 791                 .ctrlbit        = (1 << 8),
 792         }, {
 793                 .name           = SYSMMU_CLOCK_NAME,
 794                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 795                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 796                 .ctrlbit        = (1 << 9),
 797         }, {
 798                 .name           = SYSMMU_CLOCK_NAME,
 799                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 800                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 801                 .ctrlbit        = (1 << 10),
 802         }, {
 803                 .name           = SYSMMU_CLOCK_NAME,
 804                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 805                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 806                 .ctrlbit        = (0x3F << 8),
 807         }, {
 808                 .name           = SYSMMU_CLOCK_NAME2,
 809                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 810                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 811                 .ctrlbit        = (0xF << 4),
 812         }, {
 813                 .name           = SYSMMU_CLOCK_NAME,
 814                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 815                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 816                 .ctrlbit        = (1 << 11),
 817         }, {
 818                 .name           = SYSMMU_CLOCK_NAME,
 819                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 820                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 821                 .ctrlbit        = (1 << 12),
 822         }, {
 823                 .name           = SYSMMU_CLOCK_NAME,
 824                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 825                 .enable         = &exynos5_clk_ip_acp_ctrl,
 826                 .ctrlbit        = (1 << 7)
 827         }
 828 };
 829
 830 static struct clk exynos5_init_clocks_on[] = {
 831         {
 832                 .name           = "uart",
 833                 .devname        = "s5pv210-uart.0",
 834                 .enable         = exynos5_clk_ip_peric_ctrl,
 835                 .ctrlbit        = (1 << 0),
 836         }, {
 837                 .name           = "uart",
 838                 .devname        = "s5pv210-uart.1",
 839                 .enable         = exynos5_clk_ip_peric_ctrl,
 840                 .ctrlbit        = (1 << 1),
 841         }, {
 842                 .name           = "uart",
 843                 .devname        = "s5pv210-uart.2",
 844                 .enable         = exynos5_clk_ip_peric_ctrl,
 845                 .ctrlbit        = (1 << 2),
 846         }, {
 847                 .name           = "uart",
 848                 .devname        = "s5pv210-uart.3",
 849                 .enable         = exynos5_clk_ip_peric_ctrl,
 850                 .ctrlbit        = (1 << 3),
 851         }, {
 852                 .name           = "uart",
 853                 .devname        = "s5pv210-uart.4",
 854                 .enable         = exynos5_clk_ip_peric_ctrl,
 855                 .ctrlbit        = (1 << 4),
 856         }, {
 857                 .name           = "uart",
 858                 .devname        = "s5pv210-uart.5",
 859                 .enable         = exynos5_clk_ip_peric_ctrl,
 860                 .ctrlbit        = (1 << 5),
 861         }
 862 };
 863
 864 static struct clk exynos5_clk_pdma0 = {
 865         .name           = "dma",
 866         .devname        = "dma-pl330.0",
 867         .enable         = exynos5_clk_ip_fsys_ctrl,
 868         .ctrlbit        = (1 << 1),
 869 };
 870
 871 static struct clk exynos5_clk_pdma1 = {
 872         .name           = "dma",
 873         .devname        = "dma-pl330.1",
 874         .enable         = exynos5_clk_ip_fsys_ctrl,
 875         .ctrlbit        = (1 << 2),
 876 };
 877
 878 static struct clk exynos5_clk_mdma1 = {
 879         .name           = "dma",
 880         .devname        = "dma-pl330.2",
 881         .enable         = exynos5_clk_ip_gen_ctrl,
 882         .ctrlbit        = (1 << 4),
 883 };
 884
 885 static struct clk exynos5_clk_fimd1 = {
 886         .name           = "fimd",
 887         .devname        = "exynos5-fb.1",
 888         .enable         = exynos5_clk_ip_disp1_ctrl,
 889         .ctrlbit        = (1 << 0),
 890 };
 891
 892 struct clk *exynos5_clkset_group_list[] = {
 893         [0] = &clk_ext_xtal_mux,
 894         [1] = NULL,
 895         [2] = &exynos5_clk_sclk_hdmi24m,
 896         [3] = &exynos5_clk_sclk_dptxphy,
 897         [4] = &exynos5_clk_sclk_usbphy,
 898         [5] = &exynos5_clk_sclk_hdmiphy,
 899         [6] = &exynos5_clk_mout_mpll_user.clk,
 900         [7] = &exynos5_clk_mout_epll.clk,
 901         [8] = &exynos5_clk_sclk_vpll.clk,
 902         [9] = &exynos5_clk_mout_cpll.clk,
 903 };
 904
 905 struct clksrc_sources exynos5_clkset_group = {
 906         .sources        = exynos5_clkset_group_list,
 907         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 908 };
 909
 910 /* Possible clock sources for aclk_266_gscl_sub Mux */
 911 static struct clk *clk_src_gscl_266_list[] = {
 912         [0] = &clk_ext_xtal_mux,
 913         [1] = &exynos5_clk_aclk_266.clk,
 914 };
 915
 916 static struct clksrc_sources clk_src_gscl_266 = {
 917         .sources        = clk_src_gscl_266_list,
 918         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
 919 };
 920
 921 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
 922         .clk            = {
 923                 .name           = "dout_mmc0",
 924         },
 925         .sources = &exynos5_clkset_group,
 926         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
 927         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 928 };
 929
 930 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
 931         .clk            = {
 932                 .name           = "dout_mmc1",
 933         },
 934         .sources = &exynos5_clkset_group,
 935         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
 936         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 937 };
 938
 939 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
 940         .clk            = {
 941                 .name           = "dout_mmc2",
 942         },
 943         .sources = &exynos5_clkset_group,
 944         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
 945         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 946 };
 947
 948 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
 949         .clk            = {
 950                 .name           = "dout_mmc3",
 951         },
 952         .sources = &exynos5_clkset_group,
 953         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
 954         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 955 };
 956
 957 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
 958         .clk            = {
 959                 .name           = "dout_mmc4",
 960         },
 961         .sources = &exynos5_clkset_group,
 962         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
 963         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 964 };
 965
 966 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
 967         .clk    = {
 968                 .name           = "uclk1",
 969                 .devname        = "exynos4210-uart.0",
 970                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 971                 .ctrlbit        = (1 << 0),
 972         },
 973         .sources = &exynos5_clkset_group,
 974         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
 975         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
 976 };
 977
 978 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
 979         .clk    = {
 980                 .name           = "uclk1",
 981                 .devname        = "exynos4210-uart.1",
 982                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 983                 .ctrlbit        = (1 << 4),
 984         },
 985         .sources = &exynos5_clkset_group,
 986         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
 987         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
 988 };
 989
 990 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
 991         .clk    = {
 992                 .name           = "uclk1",
 993                 .devname        = "exynos4210-uart.2",
 994                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
 995                 .ctrlbit        = (1 << 8),
 996         },
 997         .sources = &exynos5_clkset_group,
 998         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
 999         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1000 };
1001
1002 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1003         .clk    = {
1004                 .name           = "uclk1",
1005                 .devname        = "exynos4210-uart.3",
1006                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1007                 .ctrlbit        = (1 << 12),
1008         },
1009         .sources = &exynos5_clkset_group,
1010         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1011         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1012 };
1013
1014 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1015         .clk    = {
1016                 .name           = "sclk_mmc",
1017                 .devname        = "exynos4-sdhci.0",
1018                 .parent         = &exynos5_clk_dout_mmc0.clk,
1019                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1020                 .ctrlbit        = (1 << 0),
1021         },
1022         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1023 };
1024
1025 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1026         .clk    = {
1027                 .name           = "sclk_mmc",
1028                 .devname        = "exynos4-sdhci.1",
1029                 .parent         = &exynos5_clk_dout_mmc1.clk,
1030                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1031                 .ctrlbit        = (1 << 4),
1032         },
1033         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1034 };
1035
1036 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1037         .clk    = {
1038                 .name           = "sclk_mmc",
1039                 .devname        = "exynos4-sdhci.2",
1040                 .parent         = &exynos5_clk_dout_mmc2.clk,
1041                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1042                 .ctrlbit        = (1 << 8),
1043         },
1044         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1045 };
1046
1047 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1048         .clk    = {
1049                 .name           = "sclk_mmc",
1050                 .devname        = "exynos4-sdhci.3",
1051                 .parent         = &exynos5_clk_dout_mmc3.clk,
1052                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1053                 .ctrlbit        = (1 << 12),
1054         },
1055         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1056 };
1057
1058 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1059         .clk    = {
1060                 .name           = "mdout_spi",
1061                 .devname        = "exynos4210-spi.0",
1062         },
1063         .sources = &exynos5_clkset_group,
1064         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1065         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1066 };
1067
1068 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1069         .clk    = {
1070                 .name           = "mdout_spi",
1071                 .devname        = "exynos4210-spi.1",
1072         },
1073         .sources = &exynos5_clkset_group,
1074         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1075         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1076 };
1077
1078 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1079         .clk    = {
1080                 .name           = "mdout_spi",
1081                 .devname        = "exynos4210-spi.2",
1082         },
1083         .sources = &exynos5_clkset_group,
1084         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1085         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1086 };
1087
1088 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1089         .clk    = {
1090                 .name           = "sclk_spi",
1091                 .devname        = "exynos4210-spi.0",
1092                 .parent         = &exynos5_clk_mdout_spi0.clk,
1093                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1094                 .ctrlbit        = (1 << 16),
1095         },
1096         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1097 };
1098
1099 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1100         .clk    = {
1101                 .name           = "sclk_spi",
1102                 .devname        = "exynos4210-spi.1",
1103                 .parent         = &exynos5_clk_mdout_spi1.clk,
1104                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1105                 .ctrlbit        = (1 << 20),
1106         },
1107         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1108 };
1109
1110 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1111         .clk    = {
1112                 .name           = "sclk_spi",
1113                 .devname        = "exynos4210-spi.2",
1114                 .parent         = &exynos5_clk_mdout_spi2.clk,
1115                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1116                 .ctrlbit        = (1 << 24),
1117         },
1118         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1119 };
1120
1121 struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1122         .clk    = {
1123                 .name           = "sclk_fimd",
1124                 .devname        = "exynos5-fb.1",
1125                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1126                 .ctrlbit        = (1 << 0),
1127         },
1128         .sources = &exynos5_clkset_group,
1129         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1130         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1131 };
1132
1133 static struct clksrc_clk exynos5_clksrcs[] = {
1134         {
1135                 .clk    = {
1136                         .name           = "sclk_dwmci",
1137                         .parent         = &exynos5_clk_dout_mmc4.clk,
1138                         .enable         = exynos5_clksrc_mask_fsys_ctrl,
1139                         .ctrlbit        = (1 << 16),
1140                 },
1141                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1142         }, {
1143                 .clk    = {
1144                         .name           = "aclk_266_gscl",
1145                 },
1146                 .sources = &clk_src_gscl_266,
1147                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1148         }, {
1149                 .clk    = {
1150                         .name           = "sclk_g3d",
1151                         .devname        = "mali-t604.0",
1152                         .enable         = exynos5_clk_block_ctrl,
1153                         .ctrlbit        = (1 << 1),
1154                 },
1155                 .sources = &exynos5_clkset_aclk,
1156                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1157                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1158         }, {
1159                 .clk    = {
1160                         .name           = "sclk_gscl_wrap",
1161                         .devname        = "s5p-mipi-csis.0",
1162                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1163                         .ctrlbit        = (1 << 24),
1164                 },
1165                 .sources = &exynos5_clkset_group,
1166                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1167                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1168         }, {
1169                 .clk    = {
1170                         .name           = "sclk_gscl_wrap",
1171                         .devname        = "s5p-mipi-csis.1",
1172                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1173                         .ctrlbit        = (1 << 28),
1174                 },
1175                 .sources = &exynos5_clkset_group,
1176                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1177                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1178         }, {
1179                 .clk    = {
1180                         .name           = "sclk_cam0",
1181                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1182                         .ctrlbit        = (1 << 16),
1183                 },
1184                 .sources = &exynos5_clkset_group,
1185                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1186                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1187         }, {
1188                 .clk    = {
1189                         .name           = "sclk_cam1",
1190                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1191                         .ctrlbit        = (1 << 20),
1192                 },
1193                 .sources = &exynos5_clkset_group,
1194                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1195                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1196         }, {
1197                 .clk    = {
1198                         .name           = "sclk_jpeg",
1199                         .parent         = &exynos5_clk_mout_cpll.clk,
1200                 },
1201                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1202         },
1203 };
1204
1205 /* Clock initialization code */
1206 static struct clksrc_clk *exynos5_sysclks[] = {
1207         &exynos5_clk_mout_apll,
1208         &exynos5_clk_sclk_apll,
1209         &exynos5_clk_mout_bpll,
1210         &exynos5_clk_mout_bpll_fout,
1211         &exynos5_clk_mout_bpll_user,
1212         &exynos5_clk_mout_cpll,
1213         &exynos5_clk_mout_epll,
1214         &exynos5_clk_mout_mpll,
1215         &exynos5_clk_mout_mpll_fout,
1216         &exynos5_clk_mout_mpll_user,
1217         &exynos5_clk_vpllsrc,
1218         &exynos5_clk_sclk_vpll,
1219         &exynos5_clk_mout_cpu,
1220         &exynos5_clk_dout_armclk,
1221         &exynos5_clk_dout_arm2clk,
1222         &exynos5_clk_cdrex,
1223         &exynos5_clk_aclk_400,
1224         &exynos5_clk_aclk_333,
1225         &exynos5_clk_aclk_266,
1226         &exynos5_clk_aclk_200,
1227         &exynos5_clk_aclk_166,
1228         &exynos5_clk_aclk_66_pre,
1229         &exynos5_clk_aclk_66,
1230         &exynos5_clk_dout_mmc0,
1231         &exynos5_clk_dout_mmc1,
1232         &exynos5_clk_dout_mmc2,
1233         &exynos5_clk_dout_mmc3,
1234         &exynos5_clk_dout_mmc4,
1235         &exynos5_clk_aclk_acp,
1236         &exynos5_clk_pclk_acp,
1237         &exynos5_clk_sclk_spi0,
1238         &exynos5_clk_sclk_spi1,
1239         &exynos5_clk_sclk_spi2,
1240         &exynos5_clk_mdout_spi0,
1241         &exynos5_clk_mdout_spi1,
1242         &exynos5_clk_mdout_spi2,
1243         &exynos5_clk_sclk_fimd1,
1244 };
1245
1246 static struct clk *exynos5_clk_cdev[] = {
1247         &exynos5_clk_pdma0,
1248         &exynos5_clk_pdma1,
1249         &exynos5_clk_mdma1,
1250         &exynos5_clk_fimd1,
1251 };
1252
1253 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1254         &exynos5_clk_sclk_uart0,
1255         &exynos5_clk_sclk_uart1,
1256         &exynos5_clk_sclk_uart2,
1257         &exynos5_clk_sclk_uart3,
1258         &exynos5_clk_sclk_mmc0,
1259         &exynos5_clk_sclk_mmc1,
1260         &exynos5_clk_sclk_mmc2,
1261         &exynos5_clk_sclk_mmc3,
1262 };
1263
1264 static struct clk_lookup exynos5_clk_lookup[] = {
1265         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1266         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1267         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1268         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1269         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1270         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1271         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1272         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1273         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1274         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1275         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1276         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1277         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1278         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1279         CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1280 };
1281
1282 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1283 {
1284         return clk->rate;
1285 }
1286
1287 static struct clk *exynos5_clks[] __initdata = {
1288         &exynos5_clk_sclk_hdmi27m,
1289         &exynos5_clk_sclk_hdmiphy,
1290         &clk_fout_bpll,
1291         &clk_fout_bpll_div2,
1292         &clk_fout_cpll,
1293         &clk_fout_mpll_div2,
1294         &exynos5_clk_armclk,
1295 };
1296
1297 static u32 epll_div[][6] = {
1298         { 192000000, 0, 48, 3, 1, 0 },
1299         { 180000000, 0, 45, 3, 1, 0 },
1300         {  73728000, 1, 73, 3, 3, 47710 },
1301         {  67737600, 1, 90, 4, 3, 20762 },
1302         {  49152000, 0, 49, 3, 3, 9961 },
1303         {  45158400, 0, 45, 3, 3, 10381 },
1304         { 180633600, 0, 45, 3, 1, 10381 },
1305 };
1306
1307 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1308 {
1309         unsigned int epll_con, epll_con_k;
1310         unsigned int i;
1311         unsigned int tmp;
1312         unsigned int epll_rate;
1313         unsigned int locktime;
1314         unsigned int lockcnt;
1315
1316         /* Return if nothing changed */
1317         if (clk->rate == rate)
1318                 return 0;
1319
1320         if (clk->parent)
1321                 epll_rate = clk_get_rate(clk->parent);
1322         else
1323                 epll_rate = clk_ext_xtal_mux.rate;
1324
1325         if (epll_rate != 24000000) {
1326                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1327                 return -EINVAL;
1328         }
1329
1330         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1331         epll_con &= ~(0x1 << 27 | \
1332                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1333                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1334                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1335
1336         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1337                 if (epll_div[i][0] == rate) {
1338                         epll_con_k = epll_div[i][5] << 0;
1339                         epll_con |= epll_div[i][1] << 27;
1340                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1341                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1342                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1343                         break;
1344                 }
1345         }
1346
1347         if (i == ARRAY_SIZE(epll_div)) {
1348                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1349                                 __func__);
1350                 return -EINVAL;
1351         }
1352
1353         epll_rate /= 1000000;
1354
1355         /* 3000 max_cycls : specification data */
1356         locktime = 3000 / epll_rate * epll_div[i][3];
1357         lockcnt = locktime * 10000 / (10000 / epll_rate);
1358
1359         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1360
1361         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1362         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1363
1364         do {
1365                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1366         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1367
1368         clk->rate = rate;
1369
1370         return 0;
1371 }
1372
1373 static struct clk_ops exynos5_epll_ops = {
1374         .get_rate = exynos5_epll_get_rate,
1375         .set_rate = exynos5_epll_set_rate,
1376 };
1377
1378 static int xtal_rate;
1379
1380 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1381 {
1382         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1383 }
1384
1385 static struct clk_ops exynos5_fout_apll_ops = {
1386         .get_rate = exynos5_fout_apll_get_rate,
1387 };
1388
1389 #ifdef CONFIG_PM
1390 static int exynos5_clock_suspend(void)
1391 {
1392         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1393
1394         return 0;
1395 }
1396
1397 static void exynos5_clock_resume(void)
1398 {
1399         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1400 }
1401 #else
1402 #define exynos5_clock_suspend NULL
1403 #define exynos5_clock_resume NULL
1404 #endif
1405
1406 struct syscore_ops exynos5_clock_syscore_ops = {
1407         .suspend        = exynos5_clock_suspend,
1408         .resume         = exynos5_clock_resume,
1409 };
1410
1411 void __init_or_cpufreq exynos5_setup_clocks(void)
1412 {
1413         struct clk *xtal_clk;
1414         unsigned long apll;
1415         unsigned long bpll;
1416         unsigned long cpll;
1417         unsigned long mpll;
1418         unsigned long epll;
1419         unsigned long vpll;
1420         unsigned long vpllsrc;
1421         unsigned long xtal;
1422         unsigned long armclk;
1423         unsigned long mout_cdrex;
1424         unsigned long aclk_400;
1425         unsigned long aclk_333;
1426         unsigned long aclk_266;
1427         unsigned long aclk_200;
1428         unsigned long aclk_166;
1429         unsigned long aclk_66;
1430         unsigned int ptr;
1431
1432         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1433
1434         xtal_clk = clk_get(NULL, "xtal");
1435         BUG_ON(IS_ERR(xtal_clk));
1436
1437         xtal = clk_get_rate(xtal_clk);
1438
1439         xtal_rate = xtal;
1440
1441         clk_put(xtal_clk);
1442
1443         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1444
1445         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1446         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1447         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1448         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1449         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1450                         __raw_readl(EXYNOS5_EPLL_CON1));
1451
1452         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1453         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1454                         __raw_readl(EXYNOS5_VPLL_CON1));
1455
1456         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1457         clk_fout_bpll.rate = bpll;
1458         clk_fout_bpll_div2.rate = bpll >> 1;
1459         clk_fout_cpll.rate = cpll;
1460         clk_fout_mpll.rate = mpll;
1461         clk_fout_mpll_div2.rate = mpll >> 1;
1462         clk_fout_epll.rate = epll;
1463         clk_fout_vpll.rate = vpll;
1464
1465         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1466                         "M=%ld, E=%ld V=%ld",
1467                         apll, bpll, cpll, mpll, epll, vpll);
1468
1469         armclk = clk_get_rate(&exynos5_clk_armclk);
1470         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1471
1472         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1473         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1474         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1475         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1476         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1477         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1478
1479         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1480                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1481                         "ACLK166=%ld, ACLK66=%ld\n",
1482                         armclk, mout_cdrex, aclk_400,
1483                         aclk_333, aclk_266, aclk_200,
1484                         aclk_166, aclk_66);
1485
1486
1487         clk_fout_epll.ops = &exynos5_epll_ops;
1488
1489         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1490                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1491                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1492
1493         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1494         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1495
1496         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1497         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1498
1499         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1500                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1501 }
1502
1503 void __init exynos5_register_clocks(void)
1504 {
1505         int ptr;
1506
1507         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1508
1509         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1510                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1511
1512         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1513                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1514
1515         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1516                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1517
1518         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1519         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1520
1521         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1522         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1523                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1524
1525         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1526         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1527         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1528
1529         register_syscore_ops(&exynos5_clock_syscore_ops);
1530         s3c_pwmclk_init();
1531 }