1 // SPDX-License-Identifier: GPL-2.0+
3 * National Semiconductor DP83848 PHY Driver for TI DaVinci
4 * (TMS320DM644x) based boards.
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * --------------------------------------------------------
14 #include <asm/arch/emac_defs.h>
15 #include "../../../drivers/net/ti/davinci_emac.h"
17 #ifdef CONFIG_DRIVER_TI_EMAC
21 int dp83848_is_phy_connected(int phy_addr)
25 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
27 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
30 if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
36 int dp83848_get_link_speed(int phy_addr)
39 volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
41 if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
44 if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
47 if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
50 /* Speed doesn't matter, there is no setting for it in EMAC... */
51 if (tmp & DP83848_DUPLEX) {
52 /* set DM644x EMAC for Full Duplex */
53 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
54 EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
56 /*set DM644x EMAC for Half Duplex */
57 emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
64 int dp83848_init_phy(int phy_addr)
68 if (!dp83848_get_link_speed(phy_addr)) {
69 /* Try another time */
71 ret = dp83848_get_link_speed(phy_addr);
74 /* Disable PHY Interrupts */
75 davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
81 int dp83848_auto_negotiate(int phy_addr)
86 if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
89 /* Restart Auto_negotiation */
90 tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
91 tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
92 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
94 /* Set the Auto_negotiation Advertisement Register
95 * MII advertising for Next page, 100BaseTxFD and HD,
96 * 10BaseTFD and HD, IEEE 802.3
98 tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
99 DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
100 davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
103 /* Read Control Register */
104 if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
107 tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
108 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
110 /* Restart Auto_negotiation */
111 tmp |= DP83848_RESTART_AUTONEG;
112 davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
114 /*check AutoNegotiate complete */
116 if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
119 if (!(tmp & DP83848_AUTONEG_COMP))
122 return (dp83848_get_link_speed(phy_addr));
125 #endif /* CONFIG_CMD_NET */
127 #endif /* CONFIG_DRIVER_ETHER */