arch/arm/mach-davinci/dm365.c

   1 /*
   2  * TI DaVinci DM365 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/gpio.h>
  21 #include <linux/spi/spi.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include <mach/dm365.h>
  26 #include <mach/cputype.h>
  27 #include <mach/edma.h>
  28 #include <mach/psc.h>
  29 #include <mach/mux.h>
  30 #include <mach/irqs.h>
  31 #include <mach/time.h>
  32 #include <mach/serial.h>
  33 #include <mach/common.h>
  34 #include <mach/asp.h>
  35 #include <mach/keyscan.h>
  36 #include <mach/spi.h>
  37
  38
  39 #include "clock.h"
  40 #include "mux.h"
  41
  42 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  43
  44 static struct pll_data pll1_data = {
  45         .num            = 1,
  46         .phys_base      = DAVINCI_PLL1_BASE,
  47         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  48 };
  49
  50 static struct pll_data pll2_data = {
  51         .num            = 2,
  52         .phys_base      = DAVINCI_PLL2_BASE,
  53         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  54 };
  55
  56 static struct clk ref_clk = {
  57         .name           = "ref_clk",
  58         .rate           = DM365_REF_FREQ,
  59 };
  60
  61 static struct clk pll1_clk = {
  62         .name           = "pll1",
  63         .parent         = &ref_clk,
  64         .flags          = CLK_PLL,
  65         .pll_data       = &pll1_data,
  66 };
  67
  68 static struct clk pll1_aux_clk = {
  69         .name           = "pll1_aux_clk",
  70         .parent         = &pll1_clk,
  71         .flags          = CLK_PLL | PRE_PLL,
  72 };
  73
  74 static struct clk pll1_sysclkbp = {
  75         .name           = "pll1_sysclkbp",
  76         .parent         = &pll1_clk,
  77         .flags          = CLK_PLL | PRE_PLL,
  78         .div_reg        = BPDIV
  79 };
  80
  81 static struct clk clkout0_clk = {
  82         .name           = "clkout0",
  83         .parent         = &pll1_clk,
  84         .flags          = CLK_PLL | PRE_PLL,
  85 };
  86
  87 static struct clk pll1_sysclk1 = {
  88         .name           = "pll1_sysclk1",
  89         .parent         = &pll1_clk,
  90         .flags          = CLK_PLL,
  91         .div_reg        = PLLDIV1,
  92 };
  93
  94 static struct clk pll1_sysclk2 = {
  95         .name           = "pll1_sysclk2",
  96         .parent         = &pll1_clk,
  97         .flags          = CLK_PLL,
  98         .div_reg        = PLLDIV2,
  99 };
 100
 101 static struct clk pll1_sysclk3 = {
 102         .name           = "pll1_sysclk3",
 103         .parent         = &pll1_clk,
 104         .flags          = CLK_PLL,
 105         .div_reg        = PLLDIV3,
 106 };
 107
 108 static struct clk pll1_sysclk4 = {
 109         .name           = "pll1_sysclk4",
 110         .parent         = &pll1_clk,
 111         .flags          = CLK_PLL,
 112         .div_reg        = PLLDIV4,
 113 };
 114
 115 static struct clk pll1_sysclk5 = {
 116         .name           = "pll1_sysclk5",
 117         .parent         = &pll1_clk,
 118         .flags          = CLK_PLL,
 119         .div_reg        = PLLDIV5,
 120 };
 121
 122 static struct clk pll1_sysclk6 = {
 123         .name           = "pll1_sysclk6",
 124         .parent         = &pll1_clk,
 125         .flags          = CLK_PLL,
 126         .div_reg        = PLLDIV6,
 127 };
 128
 129 static struct clk pll1_sysclk7 = {
 130         .name           = "pll1_sysclk7",
 131         .parent         = &pll1_clk,
 132         .flags          = CLK_PLL,
 133         .div_reg        = PLLDIV7,
 134 };
 135
 136 static struct clk pll1_sysclk8 = {
 137         .name           = "pll1_sysclk8",
 138         .parent         = &pll1_clk,
 139         .flags          = CLK_PLL,
 140         .div_reg        = PLLDIV8,
 141 };
 142
 143 static struct clk pll1_sysclk9 = {
 144         .name           = "pll1_sysclk9",
 145         .parent         = &pll1_clk,
 146         .flags          = CLK_PLL,
 147         .div_reg        = PLLDIV9,
 148 };
 149
 150 static struct clk pll2_clk = {
 151         .name           = "pll2",
 152         .parent         = &ref_clk,
 153         .flags          = CLK_PLL,
 154         .pll_data       = &pll2_data,
 155 };
 156
 157 static struct clk pll2_aux_clk = {
 158         .name           = "pll2_aux_clk",
 159         .parent         = &pll2_clk,
 160         .flags          = CLK_PLL | PRE_PLL,
 161 };
 162
 163 static struct clk clkout1_clk = {
 164         .name           = "clkout1",
 165         .parent         = &pll2_clk,
 166         .flags          = CLK_PLL | PRE_PLL,
 167 };
 168
 169 static struct clk pll2_sysclk1 = {
 170         .name           = "pll2_sysclk1",
 171         .parent         = &pll2_clk,
 172         .flags          = CLK_PLL,
 173         .div_reg        = PLLDIV1,
 174 };
 175
 176 static struct clk pll2_sysclk2 = {
 177         .name           = "pll2_sysclk2",
 178         .parent         = &pll2_clk,
 179         .flags          = CLK_PLL,
 180         .div_reg        = PLLDIV2,
 181 };
 182
 183 static struct clk pll2_sysclk3 = {
 184         .name           = "pll2_sysclk3",
 185         .parent         = &pll2_clk,
 186         .flags          = CLK_PLL,
 187         .div_reg        = PLLDIV3,
 188 };
 189
 190 static struct clk pll2_sysclk4 = {
 191         .name           = "pll2_sysclk4",
 192         .parent         = &pll2_clk,
 193         .flags          = CLK_PLL,
 194         .div_reg        = PLLDIV4,
 195 };
 196
 197 static struct clk pll2_sysclk5 = {
 198         .name           = "pll2_sysclk5",
 199         .parent         = &pll2_clk,
 200         .flags          = CLK_PLL,
 201         .div_reg        = PLLDIV5,
 202 };
 203
 204 static struct clk pll2_sysclk6 = {
 205         .name           = "pll2_sysclk6",
 206         .parent         = &pll2_clk,
 207         .flags          = CLK_PLL,
 208         .div_reg        = PLLDIV6,
 209 };
 210
 211 static struct clk pll2_sysclk7 = {
 212         .name           = "pll2_sysclk7",
 213         .parent         = &pll2_clk,
 214         .flags          = CLK_PLL,
 215         .div_reg        = PLLDIV7,
 216 };
 217
 218 static struct clk pll2_sysclk8 = {
 219         .name           = "pll2_sysclk8",
 220         .parent         = &pll2_clk,
 221         .flags          = CLK_PLL,
 222         .div_reg        = PLLDIV8,
 223 };
 224
 225 static struct clk pll2_sysclk9 = {
 226         .name           = "pll2_sysclk9",
 227         .parent         = &pll2_clk,
 228         .flags          = CLK_PLL,
 229         .div_reg        = PLLDIV9,
 230 };
 231
 232 static struct clk vpss_dac_clk = {
 233         .name           = "vpss_dac",
 234         .parent         = &pll1_sysclk3,
 235         .lpsc           = DM365_LPSC_DAC_CLK,
 236 };
 237
 238 static struct clk vpss_master_clk = {
 239         .name           = "vpss_master",
 240         .parent         = &pll1_sysclk5,
 241         .lpsc           = DM365_LPSC_VPSSMSTR,
 242         .flags          = CLK_PSC,
 243 };
 244
 245 static struct clk arm_clk = {
 246         .name           = "arm_clk",
 247         .parent         = &pll2_sysclk2,
 248         .lpsc           = DAVINCI_LPSC_ARM,
 249         .flags          = ALWAYS_ENABLED,
 250 };
 251
 252 static struct clk uart0_clk = {
 253         .name           = "uart0",
 254         .parent         = &pll1_aux_clk,
 255         .lpsc           = DAVINCI_LPSC_UART0,
 256 };
 257
 258 static struct clk uart1_clk = {
 259         .name           = "uart1",
 260         .parent         = &pll1_sysclk4,
 261         .lpsc           = DAVINCI_LPSC_UART1,
 262 };
 263
 264 static struct clk i2c_clk = {
 265         .name           = "i2c",
 266         .parent         = &pll1_aux_clk,
 267         .lpsc           = DAVINCI_LPSC_I2C,
 268 };
 269
 270 static struct clk mmcsd0_clk = {
 271         .name           = "mmcsd0",
 272         .parent         = &pll1_sysclk8,
 273         .lpsc           = DAVINCI_LPSC_MMC_SD,
 274 };
 275
 276 static struct clk mmcsd1_clk = {
 277         .name           = "mmcsd1",
 278         .parent         = &pll1_sysclk4,
 279         .lpsc           = DM365_LPSC_MMC_SD1,
 280 };
 281
 282 static struct clk spi0_clk = {
 283         .name           = "spi0",
 284         .parent         = &pll1_sysclk4,
 285         .lpsc           = DAVINCI_LPSC_SPI,
 286 };
 287
 288 static struct clk spi1_clk = {
 289         .name           = "spi1",
 290         .parent         = &pll1_sysclk4,
 291         .lpsc           = DM365_LPSC_SPI1,
 292 };
 293
 294 static struct clk spi2_clk = {
 295         .name           = "spi2",
 296         .parent         = &pll1_sysclk4,
 297         .lpsc           = DM365_LPSC_SPI2,
 298 };
 299
 300 static struct clk spi3_clk = {
 301         .name           = "spi3",
 302         .parent         = &pll1_sysclk4,
 303         .lpsc           = DM365_LPSC_SPI3,
 304 };
 305
 306 static struct clk spi4_clk = {
 307         .name           = "spi4",
 308         .parent         = &pll1_aux_clk,
 309         .lpsc           = DM365_LPSC_SPI4,
 310 };
 311
 312 static struct clk gpio_clk = {
 313         .name           = "gpio",
 314         .parent         = &pll1_sysclk4,
 315         .lpsc           = DAVINCI_LPSC_GPIO,
 316 };
 317
 318 static struct clk aemif_clk = {
 319         .name           = "aemif",
 320         .parent         = &pll1_sysclk4,
 321         .lpsc           = DAVINCI_LPSC_AEMIF,
 322 };
 323
 324 static struct clk pwm0_clk = {
 325         .name           = "pwm0",
 326         .parent         = &pll1_aux_clk,
 327         .lpsc           = DAVINCI_LPSC_PWM0,
 328 };
 329
 330 static struct clk pwm1_clk = {
 331         .name           = "pwm1",
 332         .parent         = &pll1_aux_clk,
 333         .lpsc           = DAVINCI_LPSC_PWM1,
 334 };
 335
 336 static struct clk pwm2_clk = {
 337         .name           = "pwm2",
 338         .parent         = &pll1_aux_clk,
 339         .lpsc           = DAVINCI_LPSC_PWM2,
 340 };
 341
 342 static struct clk pwm3_clk = {
 343         .name           = "pwm3",
 344         .parent         = &ref_clk,
 345         .lpsc           = DM365_LPSC_PWM3,
 346 };
 347
 348 static struct clk timer0_clk = {
 349         .name           = "timer0",
 350         .parent         = &pll1_aux_clk,
 351         .lpsc           = DAVINCI_LPSC_TIMER0,
 352 };
 353
 354 static struct clk timer1_clk = {
 355         .name           = "timer1",
 356         .parent         = &pll1_aux_clk,
 357         .lpsc           = DAVINCI_LPSC_TIMER1,
 358 };
 359
 360 static struct clk timer2_clk = {
 361         .name           = "timer2",
 362         .parent         = &pll1_aux_clk,
 363         .lpsc           = DAVINCI_LPSC_TIMER2,
 364         .usecount       = 1,
 365 };
 366
 367 static struct clk timer3_clk = {
 368         .name           = "timer3",
 369         .parent         = &pll1_aux_clk,
 370         .lpsc           = DM365_LPSC_TIMER3,
 371 };
 372
 373 static struct clk usb_clk = {
 374         .name           = "usb",
 375         .parent         = &pll1_aux_clk,
 376         .lpsc           = DAVINCI_LPSC_USB,
 377 };
 378
 379 static struct clk emac_clk = {
 380         .name           = "emac",
 381         .parent         = &pll1_sysclk4,
 382         .lpsc           = DM365_LPSC_EMAC,
 383 };
 384
 385 static struct clk voicecodec_clk = {
 386         .name           = "voice_codec",
 387         .parent         = &pll2_sysclk4,
 388         .lpsc           = DM365_LPSC_VOICE_CODEC,
 389 };
 390
 391 static struct clk asp0_clk = {
 392         .name           = "asp0",
 393         .parent         = &pll1_sysclk4,
 394         .lpsc           = DM365_LPSC_McBSP1,
 395 };
 396
 397 static struct clk rto_clk = {
 398         .name           = "rto",
 399         .parent         = &pll1_sysclk4,
 400         .lpsc           = DM365_LPSC_RTO,
 401 };
 402
 403 static struct clk mjcp_clk = {
 404         .name           = "mjcp",
 405         .parent         = &pll1_sysclk3,
 406         .lpsc           = DM365_LPSC_MJCP,
 407 };
 408
 409 static struct clk_lookup dm365_clks[] = {
 410         CLK(NULL, "ref", &ref_clk),
 411         CLK(NULL, "pll1", &pll1_clk),
 412         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 413         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 414         CLK(NULL, "clkout0", &clkout0_clk),
 415         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 416         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 417         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 418         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 419         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 420         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
 421         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 422         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 423         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
 424         CLK(NULL, "pll2", &pll2_clk),
 425         CLK(NULL, "pll2_aux", &pll2_aux_clk),
 426         CLK(NULL, "clkout1", &clkout1_clk),
 427         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 428         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 429         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
 430         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
 431         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
 432         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
 433         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
 434         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
 435         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
 436         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 437         CLK(NULL, "vpss_master", &vpss_master_clk),
 438         CLK(NULL, "arm", &arm_clk),
 439         CLK(NULL, "uart0", &uart0_clk),
 440         CLK(NULL, "uart1", &uart1_clk),
 441         CLK("i2c_davinci.1", NULL, &i2c_clk),
 442         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 443         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 444         CLK("spi_davinci.0", NULL, &spi0_clk),
 445         CLK("spi_davinci.1", NULL, &spi1_clk),
 446         CLK("spi_davinci.2", NULL, &spi2_clk),
 447         CLK("spi_davinci.3", NULL, &spi3_clk),
 448         CLK("spi_davinci.4", NULL, &spi4_clk),
 449         CLK(NULL, "gpio", &gpio_clk),
 450         CLK(NULL, "aemif", &aemif_clk),
 451         CLK(NULL, "pwm0", &pwm0_clk),
 452         CLK(NULL, "pwm1", &pwm1_clk),
 453         CLK(NULL, "pwm2", &pwm2_clk),
 454         CLK(NULL, "pwm3", &pwm3_clk),
 455         CLK(NULL, "timer0", &timer0_clk),
 456         CLK(NULL, "timer1", &timer1_clk),
 457         CLK("watchdog", NULL, &timer2_clk),
 458         CLK(NULL, "timer3", &timer3_clk),
 459         CLK(NULL, "usb", &usb_clk),
 460         CLK("davinci_emac.1", NULL, &emac_clk),
 461         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
 462         CLK("davinci-mcbsp", NULL, &asp0_clk),
 463         CLK(NULL, "rto", &rto_clk),
 464         CLK(NULL, "mjcp", &mjcp_clk),
 465         CLK(NULL, NULL, NULL),
 466 };
 467
 468 /*----------------------------------------------------------------------*/
 469
 470 #define INTMUX          0x18
 471 #define EVTMUX          0x1c
 472
 473
 474 static const struct mux_config dm365_pins[] = {
 475 #ifdef CONFIG_DAVINCI_MUX
 476 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
 477
 478 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
 479 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
 480 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
 481 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
 482 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
 483 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
 484
 485 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
 486 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
 487
 488 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
 489 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
 490 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
 491 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
 492 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
 493 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
 494 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
 495 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
 496
 497 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
 498 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
 499 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
 500 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
 501 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
 502 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
 503
 504 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
 505 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
 506 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
 507 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
 508 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
 509
 510 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
 511 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
 512 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
 513 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
 514 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
 515 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
 516
 517 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
 518 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 519 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 520 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 521 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 522 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 523 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 524 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 525 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 526 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 527 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 528 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 529 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 530 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 531 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 532 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 533 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 534
 535 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 536
 537 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 538 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 539 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 540 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 541 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 542 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 543 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 544 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 545 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 546 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 547 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 548 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 549
 550 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 551 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 552 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 553 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 554 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 555
 556 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 557 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 558 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 559 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 560 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 561
 562 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 563 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 564 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 565 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 566 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 567
 568 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 569 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 570 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 571 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 572 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 573
 574 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 575 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 576 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 577
 578 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 579 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 580 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 581 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 582 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 583 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 584 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 585
 586 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 587 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 588 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 589 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 590 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 591 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 592 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 593 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 594 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 595 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 596
 597 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 598 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 599 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 600 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 601 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 602 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 603 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 604 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 605 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 606 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 607 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 608 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 609 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 610 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 611 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 612 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 613 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 614 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 615
 616 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 617 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 618 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 619 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 620 #endif
 621 };
 622
 623 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 624
 625 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 626         .version        = SPI_VERSION_1,
 627         .num_chipselect = 2,
 628         .dma_event_q    = EVENTQ_3,
 629 };
 630
 631 static struct resource dm365_spi0_resources[] = {
 632         {
 633                 .start = 0x01c66000,
 634                 .end   = 0x01c667ff,
 635                 .flags = IORESOURCE_MEM,
 636         },
 637         {
 638                 .start = IRQ_DM365_SPIINT0_0,
 639                 .flags = IORESOURCE_IRQ,
 640         },
 641         {
 642                 .start = 17,
 643                 .flags = IORESOURCE_DMA,
 644         },
 645         {
 646                 .start = 16,
 647                 .flags = IORESOURCE_DMA,
 648         },
 649 };
 650
 651 static struct platform_device dm365_spi0_device = {
 652         .name = "spi_davinci",
 653         .id = 0,
 654         .dev = {
 655                 .dma_mask = &dm365_spi0_dma_mask,
 656                 .coherent_dma_mask = DMA_BIT_MASK(32),
 657                 .platform_data = &dm365_spi0_pdata,
 658         },
 659         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 660         .resource = dm365_spi0_resources,
 661 };
 662
 663 void __init dm365_init_spi0(unsigned chipselect_mask,
 664                 struct spi_board_info *info, unsigned len)
 665 {
 666         davinci_cfg_reg(DM365_SPI0_SCLK);
 667         davinci_cfg_reg(DM365_SPI0_SDI);
 668         davinci_cfg_reg(DM365_SPI0_SDO);
 669
 670         /* not all slaves will be wired up */
 671         if (chipselect_mask & BIT(0))
 672                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 673         if (chipselect_mask & BIT(1))
 674                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 675
 676         spi_register_board_info(info, len);
 677
 678         platform_device_register(&dm365_spi0_device);
 679 }
 680
 681 static struct emac_platform_data dm365_emac_pdata = {
 682         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 683         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 684         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 685         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 686         .version                = EMAC_VERSION_2,
 687 };
 688
 689 static struct resource dm365_emac_resources[] = {
 690         {
 691                 .start  = DM365_EMAC_BASE,
 692                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 693                 .flags  = IORESOURCE_MEM,
 694         },
 695         {
 696                 .start  = IRQ_DM365_EMAC_RXTHRESH,
 697                 .end    = IRQ_DM365_EMAC_RXTHRESH,
 698                 .flags  = IORESOURCE_IRQ,
 699         },
 700         {
 701                 .start  = IRQ_DM365_EMAC_RXPULSE,
 702                 .end    = IRQ_DM365_EMAC_RXPULSE,
 703                 .flags  = IORESOURCE_IRQ,
 704         },
 705         {
 706                 .start  = IRQ_DM365_EMAC_TXPULSE,
 707                 .end    = IRQ_DM365_EMAC_TXPULSE,
 708                 .flags  = IORESOURCE_IRQ,
 709         },
 710         {
 711                 .start  = IRQ_DM365_EMAC_MISCPULSE,
 712                 .end    = IRQ_DM365_EMAC_MISCPULSE,
 713                 .flags  = IORESOURCE_IRQ,
 714         },
 715 };
 716
 717 static struct platform_device dm365_emac_device = {
 718         .name           = "davinci_emac",
 719         .id             = 1,
 720         .dev = {
 721                 .platform_data  = &dm365_emac_pdata,
 722         },
 723         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 724         .resource       = dm365_emac_resources,
 725 };
 726
 727 static struct resource dm365_mdio_resources[] = {
 728         {
 729                 .start  = DM365_EMAC_MDIO_BASE,
 730                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 731                 .flags  = IORESOURCE_MEM,
 732         },
 733 };
 734
 735 static struct platform_device dm365_mdio_device = {
 736         .name           = "davinci_mdio",
 737         .id             = 0,
 738         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 739         .resource       = dm365_mdio_resources,
 740 };
 741
 742 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 743         [IRQ_VDINT0]                    = 2,
 744         [IRQ_VDINT1]                    = 6,
 745         [IRQ_VDINT2]                    = 6,
 746         [IRQ_HISTINT]                   = 6,
 747         [IRQ_H3AINT]                    = 6,
 748         [IRQ_PRVUINT]                   = 6,
 749         [IRQ_RSZINT]                    = 6,
 750         [IRQ_DM365_INSFINT]             = 7,
 751         [IRQ_VENCINT]                   = 6,
 752         [IRQ_ASQINT]                    = 6,
 753         [IRQ_IMXINT]                    = 6,
 754         [IRQ_DM365_IMCOPINT]            = 4,
 755         [IRQ_USBINT]                    = 4,
 756         [IRQ_DM365_RTOINT]              = 7,
 757         [IRQ_DM365_TINT5]               = 7,
 758         [IRQ_DM365_TINT6]               = 5,
 759         [IRQ_CCINT0]                    = 5,
 760         [IRQ_CCERRINT]                  = 5,
 761         [IRQ_TCERRINT0]                 = 5,
 762         [IRQ_TCERRINT]                  = 7,
 763         [IRQ_PSCIN]                     = 4,
 764         [IRQ_DM365_SPINT2_1]            = 7,
 765         [IRQ_DM365_TINT7]               = 7,
 766         [IRQ_DM365_SDIOINT0]            = 7,
 767         [IRQ_MBXINT]                    = 7,
 768         [IRQ_MBRINT]                    = 7,
 769         [IRQ_MMCINT]                    = 7,
 770         [IRQ_DM365_MMCINT1]             = 7,
 771         [IRQ_DM365_PWMINT3]             = 7,
 772         [IRQ_AEMIFINT]                  = 2,
 773         [IRQ_DM365_SDIOINT1]            = 2,
 774         [IRQ_TINT0_TINT12]              = 7,
 775         [IRQ_TINT0_TINT34]              = 7,
 776         [IRQ_TINT1_TINT12]              = 7,
 777         [IRQ_TINT1_TINT34]              = 7,
 778         [IRQ_PWMINT0]                   = 7,
 779         [IRQ_PWMINT1]                   = 3,
 780         [IRQ_PWMINT2]                   = 3,
 781         [IRQ_I2C]                       = 3,
 782         [IRQ_UARTINT0]                  = 3,
 783         [IRQ_UARTINT1]                  = 3,
 784         [IRQ_DM365_RTCINT]              = 3,
 785         [IRQ_DM365_SPIINT0_0]           = 3,
 786         [IRQ_DM365_SPIINT3_0]           = 3,
 787         [IRQ_DM365_GPIO0]               = 3,
 788         [IRQ_DM365_GPIO1]               = 7,
 789         [IRQ_DM365_GPIO2]               = 4,
 790         [IRQ_DM365_GPIO3]               = 4,
 791         [IRQ_DM365_GPIO4]               = 7,
 792         [IRQ_DM365_GPIO5]               = 7,
 793         [IRQ_DM365_GPIO6]               = 7,
 794         [IRQ_DM365_GPIO7]               = 7,
 795         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 796         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 797         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 798         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 799         [IRQ_DM365_GPIO12]              = 7,
 800         [IRQ_DM365_GPIO13]              = 7,
 801         [IRQ_DM365_GPIO14]              = 7,
 802         [IRQ_DM365_GPIO15]              = 7,
 803         [IRQ_DM365_KEYINT]              = 7,
 804         [IRQ_DM365_TCERRINT2]           = 7,
 805         [IRQ_DM365_TCERRINT3]           = 7,
 806         [IRQ_DM365_EMUINT]              = 7,
 807 };
 808
 809 /* Four Transfer Controllers on DM365 */
 810 static const s8
 811 dm365_queue_tc_mapping[][2] = {
 812         /* {event queue no, TC no} */
 813         {0, 0},
 814         {1, 1},
 815         {2, 2},
 816         {3, 3},
 817         {-1, -1},
 818 };
 819
 820 static const s8
 821 dm365_queue_priority_mapping[][2] = {
 822         /* {event queue no, Priority} */
 823         {0, 7},
 824         {1, 7},
 825         {2, 7},
 826         {3, 0},
 827         {-1, -1},
 828 };
 829
 830 static struct edma_soc_info edma_cc0_info = {
 831         .n_channel              = 64,
 832         .n_region               = 4,
 833         .n_slot                 = 256,
 834         .n_tc                   = 4,
 835         .n_cc                   = 1,
 836         .queue_tc_mapping       = dm365_queue_tc_mapping,
 837         .queue_priority_mapping = dm365_queue_priority_mapping,
 838         .default_queue          = EVENTQ_3,
 839 };
 840
 841 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
 842         &edma_cc0_info,
 843 };
 844
 845 static struct resource edma_resources[] = {
 846         {
 847                 .name   = "edma_cc0",
 848                 .start  = 0x01c00000,
 849                 .end    = 0x01c00000 + SZ_64K - 1,
 850                 .flags  = IORESOURCE_MEM,
 851         },
 852         {
 853                 .name   = "edma_tc0",
 854                 .start  = 0x01c10000,
 855                 .end    = 0x01c10000 + SZ_1K - 1,
 856                 .flags  = IORESOURCE_MEM,
 857         },
 858         {
 859                 .name   = "edma_tc1",
 860                 .start  = 0x01c10400,
 861                 .end    = 0x01c10400 + SZ_1K - 1,
 862                 .flags  = IORESOURCE_MEM,
 863         },
 864         {
 865                 .name   = "edma_tc2",
 866                 .start  = 0x01c10800,
 867                 .end    = 0x01c10800 + SZ_1K - 1,
 868                 .flags  = IORESOURCE_MEM,
 869         },
 870         {
 871                 .name   = "edma_tc3",
 872                 .start  = 0x01c10c00,
 873                 .end    = 0x01c10c00 + SZ_1K - 1,
 874                 .flags  = IORESOURCE_MEM,
 875         },
 876         {
 877                 .name   = "edma0",
 878                 .start  = IRQ_CCINT0,
 879                 .flags  = IORESOURCE_IRQ,
 880         },
 881         {
 882                 .name   = "edma0_err",
 883                 .start  = IRQ_CCERRINT,
 884                 .flags  = IORESOURCE_IRQ,
 885         },
 886         /* not using TC*_ERR */
 887 };
 888
 889 static struct platform_device dm365_edma_device = {
 890         .name                   = "edma",
 891         .id                     = 0,
 892         .dev.platform_data      = dm365_edma_info,
 893         .num_resources          = ARRAY_SIZE(edma_resources),
 894         .resource               = edma_resources,
 895 };
 896
 897 static struct resource dm365_asp_resources[] = {
 898         {
 899                 .start  = DAVINCI_DM365_ASP0_BASE,
 900                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 901                 .flags  = IORESOURCE_MEM,
 902         },
 903         {
 904                 .start  = DAVINCI_DMA_ASP0_TX,
 905                 .end    = DAVINCI_DMA_ASP0_TX,
 906                 .flags  = IORESOURCE_DMA,
 907         },
 908         {
 909                 .start  = DAVINCI_DMA_ASP0_RX,
 910                 .end    = DAVINCI_DMA_ASP0_RX,
 911                 .flags  = IORESOURCE_DMA,
 912         },
 913 };
 914
 915 static struct platform_device dm365_asp_device = {
 916         .name           = "davinci-mcbsp",
 917         .id             = -1,
 918         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 919         .resource       = dm365_asp_resources,
 920 };
 921
 922 static struct resource dm365_vc_resources[] = {
 923         {
 924                 .start  = DAVINCI_DM365_VC_BASE,
 925                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 926                 .flags  = IORESOURCE_MEM,
 927         },
 928         {
 929                 .start  = DAVINCI_DMA_VC_TX,
 930                 .end    = DAVINCI_DMA_VC_TX,
 931                 .flags  = IORESOURCE_DMA,
 932         },
 933         {
 934                 .start  = DAVINCI_DMA_VC_RX,
 935                 .end    = DAVINCI_DMA_VC_RX,
 936                 .flags  = IORESOURCE_DMA,
 937         },
 938 };
 939
 940 static struct platform_device dm365_vc_device = {
 941         .name           = "davinci_voicecodec",
 942         .id             = -1,
 943         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 944         .resource       = dm365_vc_resources,
 945 };
 946
 947 static struct resource dm365_rtc_resources[] = {
 948         {
 949                 .start = DM365_RTC_BASE,
 950                 .end = DM365_RTC_BASE + SZ_1K - 1,
 951                 .flags = IORESOURCE_MEM,
 952         },
 953         {
 954                 .start = IRQ_DM365_RTCINT,
 955                 .flags = IORESOURCE_IRQ,
 956         },
 957 };
 958
 959 static struct platform_device dm365_rtc_device = {
 960         .name = "rtc_davinci",
 961         .id = 0,
 962         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
 963         .resource = dm365_rtc_resources,
 964 };
 965
 966 static struct map_desc dm365_io_desc[] = {
 967         {
 968                 .virtual        = IO_VIRT,
 969                 .pfn            = __phys_to_pfn(IO_PHYS),
 970                 .length         = IO_SIZE,
 971                 .type           = MT_DEVICE
 972         },
 973         {
 974                 .virtual        = SRAM_VIRT,
 975                 .pfn            = __phys_to_pfn(0x00010000),
 976                 .length         = SZ_32K,
 977                 .type           = MT_MEMORY_NONCACHED,
 978         },
 979 };
 980
 981 static struct resource dm365_ks_resources[] = {
 982         {
 983                 /* registers */
 984                 .start = DM365_KEYSCAN_BASE,
 985                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
 986                 .flags = IORESOURCE_MEM,
 987         },
 988         {
 989                 /* interrupt */
 990                 .start = IRQ_DM365_KEYINT,
 991                 .end = IRQ_DM365_KEYINT,
 992                 .flags = IORESOURCE_IRQ,
 993         },
 994 };
 995
 996 static struct platform_device dm365_ks_device = {
 997         .name           = "davinci_keyscan",
 998         .id             = 0,
 999         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
1000         .resource       = dm365_ks_resources,
1001 };
1002
1003 /* Contents of JTAG ID register used to identify exact cpu type */
1004 static struct davinci_id dm365_ids[] = {
1005         {
1006                 .variant        = 0x0,
1007                 .part_no        = 0xb83e,
1008                 .manufacturer   = 0x017,
1009                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1010                 .name           = "dm365_rev1.1",
1011         },
1012         {
1013                 .variant        = 0x8,
1014                 .part_no        = 0xb83e,
1015                 .manufacturer   = 0x017,
1016                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1017                 .name           = "dm365_rev1.2",
1018         },
1019 };
1020
1021 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1022
1023 static struct davinci_timer_info dm365_timer_info = {
1024         .timers         = davinci_timer_instance,
1025         .clockevent_id  = T0_BOT,
1026         .clocksource_id = T0_TOP,
1027 };
1028
1029 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
1030
1031 static struct plat_serial8250_port dm365_serial_platform_data[] = {
1032         {
1033                 .mapbase        = DAVINCI_UART0_BASE,
1034                 .irq            = IRQ_UARTINT0,
1035                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1036                                   UPF_IOREMAP,
1037                 .iotype         = UPIO_MEM,
1038                 .regshift       = 2,
1039         },
1040         {
1041                 .mapbase        = DM365_UART1_BASE,
1042                 .irq            = IRQ_UARTINT1,
1043                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1044                                   UPF_IOREMAP,
1045                 .iotype         = UPIO_MEM,
1046                 .regshift       = 2,
1047         },
1048         {
1049                 .flags          = 0
1050         },
1051 };
1052
1053 static struct platform_device dm365_serial_device = {
1054         .name                   = "serial8250",
1055         .id                     = PLAT8250_DEV_PLATFORM,
1056         .dev                    = {
1057                 .platform_data  = dm365_serial_platform_data,
1058         },
1059 };
1060
1061 static struct davinci_soc_info davinci_soc_info_dm365 = {
1062         .io_desc                = dm365_io_desc,
1063         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
1064         .jtag_id_reg            = 0x01c40028,
1065         .ids                    = dm365_ids,
1066         .ids_num                = ARRAY_SIZE(dm365_ids),
1067         .cpu_clks               = dm365_clks,
1068         .psc_bases              = dm365_psc_bases,
1069         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
1070         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1071         .pinmux_pins            = dm365_pins,
1072         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
1073         .intc_base              = DAVINCI_ARM_INTC_BASE,
1074         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1075         .intc_irq_prios         = dm365_default_priorities,
1076         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1077         .timer_info             = &dm365_timer_info,
1078         .gpio_type              = GPIO_TYPE_DAVINCI,
1079         .gpio_base              = DAVINCI_GPIO_BASE,
1080         .gpio_num               = 104,
1081         .gpio_irq               = IRQ_DM365_GPIO0,
1082         .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
1083         .serial_dev             = &dm365_serial_device,
1084         .emac_pdata             = &dm365_emac_pdata,
1085         .sram_dma               = 0x00010000,
1086         .sram_len               = SZ_32K,
1087         .reset_device           = &davinci_wdt_device,
1088 };
1089
1090 void __init dm365_init_asp(struct snd_platform_data *pdata)
1091 {
1092         davinci_cfg_reg(DM365_MCBSP0_BDX);
1093         davinci_cfg_reg(DM365_MCBSP0_X);
1094         davinci_cfg_reg(DM365_MCBSP0_BFSX);
1095         davinci_cfg_reg(DM365_MCBSP0_BDR);
1096         davinci_cfg_reg(DM365_MCBSP0_R);
1097         davinci_cfg_reg(DM365_MCBSP0_BFSR);
1098         davinci_cfg_reg(DM365_EVT2_ASP_TX);
1099         davinci_cfg_reg(DM365_EVT3_ASP_RX);
1100         dm365_asp_device.dev.platform_data = pdata;
1101         platform_device_register(&dm365_asp_device);
1102 }
1103
1104 void __init dm365_init_vc(struct snd_platform_data *pdata)
1105 {
1106         davinci_cfg_reg(DM365_EVT2_VC_TX);
1107         davinci_cfg_reg(DM365_EVT3_VC_RX);
1108         dm365_vc_device.dev.platform_data = pdata;
1109         platform_device_register(&dm365_vc_device);
1110 }
1111
1112 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1113 {
1114         dm365_ks_device.dev.platform_data = pdata;
1115         platform_device_register(&dm365_ks_device);
1116 }
1117
1118 void __init dm365_init_rtc(void)
1119 {
1120         davinci_cfg_reg(DM365_INT_PRTCSS);
1121         platform_device_register(&dm365_rtc_device);
1122 }
1123
1124 void __init dm365_init(void)
1125 {
1126         davinci_common_init(&davinci_soc_info_dm365);
1127 }
1128
1129 static struct resource dm365_vpss_resources[] = {
1130         {
1131                 /* VPSS ISP5 Base address */
1132                 .name           = "isp5",
1133                 .start          = 0x01c70000,
1134                 .end            = 0x01c70000 + 0xff,
1135                 .flags          = IORESOURCE_MEM,
1136         },
1137         {
1138                 /* VPSS CLK Base address */
1139                 .name           = "vpss",
1140                 .start          = 0x01c70200,
1141                 .end            = 0x01c70200 + 0xff,
1142                 .flags          = IORESOURCE_MEM,
1143         },
1144 };
1145
1146 static struct platform_device dm365_vpss_device = {
1147        .name                   = "vpss",
1148        .id                     = -1,
1149        .dev.platform_data      = "dm365_vpss",
1150        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
1151        .resource               = dm365_vpss_resources,
1152 };
1153
1154 static struct resource vpfe_resources[] = {
1155         {
1156                 .start          = IRQ_VDINT0,
1157                 .end            = IRQ_VDINT0,
1158                 .flags          = IORESOURCE_IRQ,
1159         },
1160         {
1161                 .start          = IRQ_VDINT1,
1162                 .end            = IRQ_VDINT1,
1163                 .flags          = IORESOURCE_IRQ,
1164         },
1165 };
1166
1167 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1168 static struct platform_device vpfe_capture_dev = {
1169         .name           = CAPTURE_DRV_NAME,
1170         .id             = -1,
1171         .num_resources  = ARRAY_SIZE(vpfe_resources),
1172         .resource       = vpfe_resources,
1173         .dev = {
1174                 .dma_mask               = &vpfe_capture_dma_mask,
1175                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1176         },
1177 };
1178
1179 static void dm365_isif_setup_pinmux(void)
1180 {
1181         davinci_cfg_reg(DM365_VIN_CAM_WEN);
1182         davinci_cfg_reg(DM365_VIN_CAM_VD);
1183         davinci_cfg_reg(DM365_VIN_CAM_HD);
1184         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1185         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1186 }
1187
1188 static struct resource isif_resource[] = {
1189         /* ISIF Base address */
1190         {
1191                 .start          = 0x01c71000,
1192                 .end            = 0x01c71000 + 0x1ff,
1193                 .flags          = IORESOURCE_MEM,
1194         },
1195         /* ISIF Linearization table 0 */
1196         {
1197                 .start          = 0x1C7C000,
1198                 .end            = 0x1C7C000 + 0x2ff,
1199                 .flags          = IORESOURCE_MEM,
1200         },
1201         /* ISIF Linearization table 1 */
1202         {
1203                 .start          = 0x1C7C400,
1204                 .end            = 0x1C7C400 + 0x2ff,
1205                 .flags          = IORESOURCE_MEM,
1206         },
1207 };
1208 static struct platform_device dm365_isif_dev = {
1209         .name           = "isif",
1210         .id             = -1,
1211         .num_resources  = ARRAY_SIZE(isif_resource),
1212         .resource       = isif_resource,
1213         .dev = {
1214                 .dma_mask               = &vpfe_capture_dma_mask,
1215                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1216                 .platform_data          = dm365_isif_setup_pinmux,
1217         },
1218 };
1219
1220 static int __init dm365_init_devices(void)
1221 {
1222         if (!cpu_is_davinci_dm365())
1223                 return 0;
1224
1225         davinci_cfg_reg(DM365_INT_EDMA_CC);
1226         platform_device_register(&dm365_edma_device);
1227
1228         platform_device_register(&dm365_mdio_device);
1229         platform_device_register(&dm365_emac_device);
1230         clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
1231                       NULL, &dm365_emac_device.dev);
1232
1233         /* Add isif clock alias */
1234         clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
1235         platform_device_register(&dm365_vpss_device);
1236         platform_device_register(&dm365_isif_dev);
1237         platform_device_register(&vpfe_capture_dev);
1238         return 0;
1239 }
1240 postcore_initcall(dm365_init_devices);
1241
1242 void dm365_set_vpfe_config(struct vpfe_config *cfg)
1243 {
1244        vpfe_capture_dev.dev.platform_data = cfg;
1245 }