arch/arm/mach-davinci/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004 Texas Instruments.
   4  * Copyright (C) 2009 David Brownell
   5  */
   6
   7 #include <config.h>
   8 #include <clock_legacy.h>
   9 #include <init.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/global_data.h>
  12 #include <asm/io.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 /* offsets from PLL controller base */
  17 #define PLLC_PLLCTL     0x100
  18 #define PLLC_PLLM       0x110
  19 #define PLLC_PREDIV     0x114
  20 #define PLLC_PLLDIV1    0x118
  21 #define PLLC_PLLDIV2    0x11c
  22 #define PLLC_PLLDIV3    0x120
  23 #define PLLC_POSTDIV    0x128
  24 #define PLLC_BPDIV      0x12c
  25 #define PLLC_PLLDIV4    0x160
  26 #define PLLC_PLLDIV5    0x164
  27 #define PLLC_PLLDIV6    0x168
  28 #define PLLC_PLLDIV7    0x16c
  29 #define PLLC_PLLDIV8    0x170
  30 #define PLLC_PLLDIV9    0x174
  31
  32 unsigned int sysdiv[9] = {
  33         PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
  34         PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
  35 };
  36
  37 int clk_get(enum davinci_clk_ids id)
  38 {
  39         int pre_div;
  40         int pllm;
  41         int post_div;
  42         int pll_out;
  43         unsigned int pll_base;
  44
  45         pll_out = CFG_SYS_OSCIN_FREQ;
  46
  47         if (id == DAVINCI_AUXCLK_CLKID)
  48                 goto out;
  49
  50         if ((id >> 16) == 1)
  51                 pll_base = (unsigned int)davinci_pllc1_regs;
  52         else
  53                 pll_base = (unsigned int)davinci_pllc0_regs;
  54
  55         id &= 0xFFFF;
  56
  57         /*
  58          * Lets keep this simple. Combining operations can result in
  59          * unexpected approximations
  60          */
  61         pre_div = (readl(pll_base + PLLC_PREDIV) &
  62                 DAVINCI_PLLC_DIV_MASK) + 1;
  63         pllm = readl(pll_base + PLLC_PLLM) + 1;
  64
  65         pll_out /= pre_div;
  66         pll_out *= pllm;
  67
  68         if (id == DAVINCI_PLLM_CLKID)
  69                 goto out;
  70
  71         post_div = (readl(pll_base + PLLC_POSTDIV) &
  72                 DAVINCI_PLLC_DIV_MASK) + 1;
  73
  74         pll_out /= post_div;
  75
  76         if (id == DAVINCI_PLLC_CLKID)
  77                 goto out;
  78
  79         pll_out /= (readl(pll_base + sysdiv[id - 1]) &
  80                 DAVINCI_PLLC_DIV_MASK) + 1;
  81
  82 out:
  83         return pll_out;
  84 }
  85
  86 int set_cpu_clk_info(void)
  87 {
  88         gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
  89         /* DDR PHY uses an x2 input clock */
  90         gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
  91                                 (clk_get(DAVINCI_DDR_CLKID) / 1000000);
  92         gd->bd->bi_dsp_freq = 0;
  93         return 0;
  94 }
  95
  96 unsigned long get_board_sys_clk(void)
  97 {
  98         return clk_get(DAVINCI_ARM_CLKID);
  99 }