4 prompt "DaVinci board select"
9 select MACH_DAVINCI_DA850_EVM
13 config TARGET_OMAPL138_LCDK
19 bool "LEGO MINDSTORMS EV3"
20 select MACH_DAVINCI_DA850_EVM
29 bool "Enable Lowlevel DA850 initialization"
32 config SYS_DA850_PLL_INIT
35 config SYS_DA850_DDR_INIT
44 select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
45 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
47 config MACH_DAVINCI_DA850_EVM
51 comment "DA850 PLL Initialization Parameters"
54 int "PLLCTL Clock Mode"
57 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
59 config SYS_DA850_PLL0_POSTDIV
60 int "PLLC0 PLL Post-Divider"
63 Value written to PLLC0 PLL Post-Divider Control Register
65 config SYS_DA850_PLL0_PLLDIV1
69 Value written to PLLC0 Divider 1 register
71 config SYS_DA850_PLL0_PLLDIV2
75 Value written to PLLC0 Divider 2 register
77 config SYS_DA850_PLL0_PLLDIV3
81 Value written to PLLC0 Divider 3 register
83 config SYS_DA850_PLL0_PLLDIV4
87 Value written to PLLC0 Divider 4 register
89 config SYS_DA850_PLL0_PLLDIV5
93 Value written to PLLC0 Divider 5 register
95 config SYS_DA850_PLL0_PLLDIV6
99 Value written to PLLC0 Divider 6 register
101 config SYS_DA850_PLL0_PLLDIV7
102 hex "PLLC0 Divider 7"
105 Value written to PLLC0 Divider 7 register
107 config SYS_DA850_PLL1_POSTDIV
108 hex "PLLC1 PLL Post-Divider"
111 Value written to PLLC1 PLL Post-Divider Control Register
113 config SYS_DA850_PLL1_PLLDIV1
114 hex "PLLC1 Divider 2"
117 Value written to PLLC1 Divider 1 register
119 config SYS_DA850_PLL1_PLLDIV2
120 hex "PLLC1 Divider 2"
123 Value written to PLLC1 Divider 2 register
125 config SYS_DA850_PLL1_PLLDIV3
126 hex "PLLC1 Divider 3"
129 Value written to PLLC1 Divider 3 register
133 source "board/davinci/da8xxevm/Kconfig"
134 source "board/lego/ev3/Kconfig"
137 default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"