2 * linux/arch/arm/mach-clps711x/core.c
4 * Core support for the CLPS711x-based machines.
6 * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/clk.h>
28 #include <linux/clkdev.h>
29 #include <linux/clockchips.h>
30 #include <linux/clk-provider.h>
32 #include <asm/exception.h>
33 #include <asm/mach/irq.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/time.h>
36 #include <asm/system_misc.h>
38 #include <mach/hardware.h>
40 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
44 * This maps the generic CLPS711x registers
46 static struct map_desc clps711x_io_desc[] __initdata = {
48 .virtual = (unsigned long)CLPS711X_VIRT_BASE,
49 .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
55 void __init clps711x_map_io(void)
57 iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
60 static void int1_mask(struct irq_data *d)
64 intmr1 = clps_readl(INTMR1);
65 intmr1 &= ~(1 << d->irq);
66 clps_writel(intmr1, INTMR1);
69 static void int1_eoi(struct irq_data *d)
72 case IRQ_CSINT: clps_writel(0, COEOI); break;
73 case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
74 case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
75 case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
76 case IRQ_TINT: clps_writel(0, TEOI); break;
77 case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
81 static void int1_unmask(struct irq_data *d)
85 intmr1 = clps_readl(INTMR1);
86 intmr1 |= 1 << d->irq;
87 clps_writel(intmr1, INTMR1);
90 static struct irq_chip int1_chip = {
91 .name = "Interrupt Vector 1",
93 .irq_mask = int1_mask,
94 .irq_unmask = int1_unmask,
97 static void int2_mask(struct irq_data *d)
101 intmr2 = clps_readl(INTMR2);
102 intmr2 &= ~(1 << (d->irq - 16));
103 clps_writel(intmr2, INTMR2);
106 static void int2_eoi(struct irq_data *d)
109 case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
113 static void int2_unmask(struct irq_data *d)
117 intmr2 = clps_readl(INTMR2);
118 intmr2 |= 1 << (d->irq - 16);
119 clps_writel(intmr2, INTMR2);
122 static struct irq_chip int2_chip = {
123 .name = "Interrupt Vector 2",
125 .irq_mask = int2_mask,
126 .irq_unmask = int2_unmask,
129 static void int3_mask(struct irq_data *d)
133 intmr3 = clps_readl(INTMR3);
134 intmr3 &= ~(1 << (d->irq - 32));
135 clps_writel(intmr3, INTMR3);
138 static void int3_unmask(struct irq_data *d)
142 intmr3 = clps_readl(INTMR3);
143 intmr3 |= 1 << (d->irq - 32);
144 clps_writel(intmr3, INTMR3);
147 static struct irq_chip int3_chip = {
148 .name = "Interrupt Vector 3",
149 .irq_mask = int3_mask,
150 .irq_unmask = int3_unmask,
155 struct irq_chip *chip;
156 irq_flow_handler_t handle;
157 } clps711x_irqdescs[] __initdata = {
158 { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
159 { IRQ_EINT1, &int1_chip, handle_level_irq, },
160 { IRQ_EINT2, &int1_chip, handle_level_irq, },
161 { IRQ_EINT3, &int1_chip, handle_level_irq, },
162 { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
163 { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
164 { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
165 { IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
166 { IRQ_UTXINT1, &int1_chip, handle_level_irq, },
167 { IRQ_URXINT1, &int1_chip, handle_level_irq, },
168 { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
169 { IRQ_SSEOTI, &int1_chip, handle_level_irq, },
170 { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
171 { IRQ_SS2RX, &int2_chip, handle_level_irq, },
172 { IRQ_SS2TX, &int2_chip, handle_level_irq, },
173 { IRQ_UTXINT2, &int2_chip, handle_level_irq, },
174 { IRQ_URXINT2, &int2_chip, handle_level_irq, },
177 void __init clps711x_init_irq(void)
181 /* Disable interrupts */
182 clps_writel(0, INTMR1);
183 clps_writel(0, INTMR2);
184 clps_writel(0, INTMR3);
186 /* Clear down any pending interrupts */
187 clps_writel(0, BLEOI);
188 clps_writel(0, MCEOI);
189 clps_writel(0, COEOI);
190 clps_writel(0, TC1EOI);
191 clps_writel(0, TC2EOI);
192 clps_writel(0, RTCEOI);
193 clps_writel(0, TEOI);
194 clps_writel(0, UMSEOI);
195 clps_writel(0, KBDEOI);
196 clps_writel(0, SRXEOF);
197 clps_writel(0xffffffff, DAISR);
199 for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
200 irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
201 clps711x_irqdescs[i].chip,
202 clps711x_irqdescs[i].handle);
203 set_irq_flags(clps711x_irqdescs[i].nr,
204 IRQF_VALID | IRQF_PROBE);
207 if (IS_ENABLED(CONFIG_FIQ)) {
209 irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
211 set_irq_flags(IRQ_DAIINT,
212 IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
216 inline u32 fls16(u32 x)
238 asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
241 void __iomem *base = CLPS711X_VIRT_BASE;
243 irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
245 handle_IRQ(fls16(irqstat), regs);
249 irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
251 handle_IRQ(fls16(irqstat) + 16, regs);
254 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
255 struct clock_event_device *evt)
259 static struct clock_event_device clockevent_clps711x = {
260 .name = "CLPS711x Clockevents",
262 .features = CLOCK_EVT_FEAT_PERIODIC,
263 .set_mode = clps711x_clockevent_set_mode,
266 static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
268 clockevent_clps711x.event_handler(&clockevent_clps711x);
273 static struct irqaction clps711x_timer_irq = {
274 .name = "CLPS711x Timer Tick",
275 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
276 .handler = clps711x_timer_interrupt,
279 static void add_fixed_clk(struct clk *clk, const char *name, int rate)
281 clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
282 clk_register_clkdev(clk, name, NULL);
285 static void __init clps711x_timer_init(void)
287 int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
293 tmp = clps_readl(PLLR) >> 24;
295 pll = (osc * tmp) / 2;
297 pll = 73728000; /* Default value */
299 tmp = clps_readl(SYSFLG2);
300 if (tmp & SYSFLG2_CKMODE) {
315 if (tmp & SYSFLG2_CKMODE) {
316 tmp = clps_readl(SYSCON2);
317 if (tmp & SYSCON2_OSTB)
326 /* All clocks are fixed */
327 add_fixed_clk(clk_pll, "pll", pll);
328 add_fixed_clk(clk_bus, "bus", bus);
329 add_fixed_clk(clk_uart, "uart", uart);
330 add_fixed_clk(clk_timerl, "timer_lf", timl);
331 add_fixed_clk(clk_timerh, "timer_hf", timh);
332 add_fixed_clk(clk_tint, "tint", 64);
333 add_fixed_clk(clk_spi, "spi", spi);
335 pr_info("CPU frequency set at %i Hz.\n", cpu);
337 clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
339 tmp = clps_readl(SYSCON1);
340 tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
341 clps_writel(tmp, SYSCON1);
343 clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
345 setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
348 struct sys_timer clps711x_timer = {
349 .init = clps711x_timer_init,
352 void clps711x_restart(char mode, const char *cmd)
357 static void clps711x_idle(void)
359 clps_writel(1, HALT);
360 __asm__ __volatile__(
365 static int __init clps711x_idle_init(void)
367 arm_pm_idle = clps711x_idle;
371 arch_initcall(clps711x_idle_init);