arch/arm/mach-bcm283x/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2012 Stephen Warren
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  */
   8
   9 #include <common.h>
  10 #include <dm/device.h>
  11 #include <fdt_support.h>
  12
  13 #ifdef CONFIG_ARM64
  14 #include <asm/armv8/mmu.h>
  15
  16 static struct mm_region bcm283x_mem_map[] = {
  17         {
  18                 .virt = 0x00000000UL,
  19                 .phys = 0x00000000UL,
  20                 .size = 0x3f000000UL,
  21                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  22                          PTE_BLOCK_INNER_SHARE
  23         }, {
  24                 .virt = 0x3f000000UL,
  25                 .phys = 0x3f000000UL,
  26                 .size = 0x01000000UL,
  27                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  28                          PTE_BLOCK_NON_SHARE |
  29                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  30         }, {
  31                 /* List terminator */
  32                 0,
  33         }
  34 };
  35
  36 static struct mm_region bcm2711_mem_map[] = {
  37         {
  38                 .virt = 0x00000000UL,
  39                 .phys = 0x00000000UL,
  40                 .size = 0xfe000000UL,
  41                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  42                          PTE_BLOCK_INNER_SHARE
  43         }, {
  44                 .virt = 0xfe000000UL,
  45                 .phys = 0xfe000000UL,
  46                 .size = 0x01800000UL,
  47                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48                          PTE_BLOCK_NON_SHARE |
  49                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  50         }, {
  51                 /* List terminator */
  52                 0,
  53         }
  54 };
  55
  56 struct mm_region *mem_map = bcm283x_mem_map;
  57
  58 /*
  59  * I/O address space varies on different chip versions.
  60  * We set the base address by inspecting the DTB.
  61  */
  62 static const struct udevice_id board_ids[] = {
  63         { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
  64         { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
  65         { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
  66         { },
  67 };
  68
  69 static void _rpi_update_mem_map(struct mm_region *pd)
  70 {
  71         int i;
  72
  73         for (i = 0; i < 2; i++) {
  74                 mem_map[i].virt = pd[i].virt;
  75                 mem_map[i].phys = pd[i].phys;
  76                 mem_map[i].size = pd[i].size;
  77                 mem_map[i].attrs = pd[i].attrs;
  78         }
  79 }
  80
  81 static void rpi_update_mem_map(void)
  82 {
  83         int ret;
  84         struct mm_region *mm;
  85         const struct udevice_id *of_match = board_ids;
  86
  87         while (of_match->compatible) {
  88                 ret = fdt_node_check_compatible(gd->fdt_blob, 0,
  89                                                 of_match->compatible);
  90                 if (!ret) {
  91                         mm = (struct mm_region *)of_match->data;
  92                         _rpi_update_mem_map(mm);
  93                         break;
  94                 }
  95
  96                 of_match++;
  97         }
  98 }
  99 #else
 100 static void rpi_update_mem_map(void) {}
 101 #endif
 102
 103 unsigned long rpi_bcm283x_base = 0x3f000000;
 104
 105 int arch_cpu_init(void)
 106 {
 107         icache_enable();
 108
 109         return 0;
 110 }
 111
 112 int mach_cpu_init(void)
 113 {
 114         int ret, soc_offset;
 115         u64 io_base, size;
 116
 117         rpi_update_mem_map();
 118
 119         /* Get IO base from device tree */
 120         soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
 121         if (soc_offset < 0)
 122                 return soc_offset;
 123
 124         ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
 125                                 &io_base, &size);
 126         if (ret)
 127                 return ret;
 128
 129         rpi_bcm283x_base = io_base;
 130
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_ARMV7_LPAE
 135 void enable_caches(void)
 136 {
 137         dcache_enable();
 138 }
 139 #endif