arch/arm/mach-bcm283x/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2012 Stephen Warren
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <init.h>
  12 #include <dm/device.h>
  13 #include <fdt_support.h>
  14 #include <asm/global_data.h>
  15
  16 #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS        0x600000000UL
  17 #define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE        0x400000UL
  18
  19 #ifdef CONFIG_ARM64
  20 #include <asm/armv8/mmu.h>
  21
  22 #define MEM_MAP_MAX_ENTRIES (4)
  23
  24 static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
  25         {
  26                 .virt = 0x00000000UL,
  27                 .phys = 0x00000000UL,
  28                 .size = 0x3f000000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  30                          PTE_BLOCK_INNER_SHARE
  31         }, {
  32                 .virt = 0x3f000000UL,
  33                 .phys = 0x3f000000UL,
  34                 .size = 0x01000000UL,
  35                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  36                          PTE_BLOCK_NON_SHARE |
  37                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  38         }, {
  39                 /* List terminator */
  40                 0,
  41         }
  42 };
  43
  44 static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
  45         {
  46                 .virt = 0x00000000UL,
  47                 .phys = 0x00000000UL,
  48                 .size = 0xfc000000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  50                          PTE_BLOCK_INNER_SHARE
  51         }, {
  52                 .virt = 0xfc000000UL,
  53                 .phys = 0xfc000000UL,
  54                 .size = 0x03800000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_NON_SHARE |
  57                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58         }, {
  59                 .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  60                 .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
  61                 .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  63                          PTE_BLOCK_NON_SHARE |
  64                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  65         }, {
  66                 /* List terminator */
  67                 0,
  68         }
  69 };
  70
  71 static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = {
  72         {
  73                 /* First 1GB of DRAM */
  74                 .virt = 0x00000000UL,
  75                 .phys = 0x00000000UL,
  76                 .size = 0x40000000UL,
  77                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  78                          PTE_BLOCK_INNER_SHARE
  79         }, {
  80                 /* Beginning of AXI bus where uSD controller lives */
  81                 .virt = 0x1000000000UL,
  82                 .phys = 0x1000000000UL,
  83                 .size = 0x0002000000UL,
  84                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  85                          PTE_BLOCK_NON_SHARE |
  86                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  87         }, {
  88                 /* SoC bus */
  89                 .virt = 0x107c000000UL,
  90                 .phys = 0x107c000000UL,
  91                 .size = 0x0004000000UL,
  92                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  93                          PTE_BLOCK_NON_SHARE |
  94                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  95         }, {
  96                 /* List terminator */
  97                 0,
  98         }
  99 };
 100
 101 struct mm_region *mem_map = bcm283x_mem_map;
 102
 103 /*
 104  * I/O address space varies on different chip versions.
 105  * We set the base address by inspecting the DTB.
 106  */
 107 static const struct udevice_id board_ids[] = {
 108         { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
 109         { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
 110         { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
 111         { .compatible = "brcm,bcm2712", .data = (ulong)&bcm2712_mem_map},
 112         { },
 113 };
 114
 115 static void _rpi_update_mem_map(struct mm_region *pd)
 116 {
 117         int i;
 118
 119         for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
 120                 mem_map[i].virt = pd[i].virt;
 121                 mem_map[i].phys = pd[i].phys;
 122                 mem_map[i].size = pd[i].size;
 123                 mem_map[i].attrs = pd[i].attrs;
 124         }
 125 }
 126
 127 static void rpi_update_mem_map(void)
 128 {
 129         int ret;
 130         struct mm_region *mm;
 131         const struct udevice_id *of_match = board_ids;
 132
 133         while (of_match->compatible) {
 134                 ret = fdt_node_check_compatible(gd->fdt_blob, 0,
 135                                                 of_match->compatible);
 136                 if (!ret) {
 137                         mm = (struct mm_region *)of_match->data;
 138                         _rpi_update_mem_map(mm);
 139                         break;
 140                 }
 141
 142                 of_match++;
 143         }
 144 }
 145 #else
 146 static void rpi_update_mem_map(void) {}
 147 #endif
 148
 149 /* Default bcm283x devices addresses */
 150 unsigned long rpi_mbox_base  = 0x3f00b880;
 151 unsigned long rpi_sdhci_base = 0x3f300000;
 152 unsigned long rpi_wdog_base  = 0x3f100000;
 153 unsigned long rpi_timer_base = 0x3f003000;
 154
 155 int arch_cpu_init(void)
 156 {
 157         icache_enable();
 158
 159         return 0;
 160 }
 161
 162 int mach_cpu_init(void)
 163 {
 164         int ret, soc, offset;
 165         u64 io_base, size;
 166
 167         rpi_update_mem_map();
 168
 169         /* Get IO base from device tree */
 170         soc = fdt_path_offset(gd->fdt_blob, "/soc");
 171         if (soc < 0)
 172                 return soc;
 173
 174         ret = fdt_read_range((void *)gd->fdt_blob, soc, 0, NULL,
 175                              &io_base, &size);
 176         if (ret)
 177                 return ret;
 178
 179         rpi_mbox_base  = io_base + 0x00b880;
 180         rpi_sdhci_base = io_base + 0x300000;
 181         rpi_wdog_base  = io_base + 0x100000;
 182         rpi_timer_base = io_base + 0x003000;
 183
 184         offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
 185                                                "brcm,bcm2835-mbox");
 186         if (offset > soc)
 187                 rpi_mbox_base = fdt_get_base_address(gd->fdt_blob, offset);
 188
 189         offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
 190                                                "brcm,bcm2835-sdhci");
 191         if (offset > soc)
 192                 rpi_sdhci_base = fdt_get_base_address(gd->fdt_blob, offset);
 193
 194         offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
 195                                                "brcm,bcm2835-system-timer");
 196         if (offset > soc)
 197                 rpi_timer_base = fdt_get_base_address(gd->fdt_blob, offset);
 198
 199         offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
 200                                                "brcm,bcm2712-pm");
 201         if (offset > soc)
 202                 rpi_wdog_base = fdt_get_base_address(gd->fdt_blob, offset);
 203
 204         return 0;
 205 }
 206
 207 #ifdef CONFIG_ARMV7_LPAE
 208 #ifdef CONFIG_TARGET_RPI_4_32B
 209 #define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT        0xffc00000UL
 210 #include <addr_map.h>
 211 #include <asm/system.h>
 212
 213 int init_addr_map(void)
 214 {
 215         mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
 216                                              BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
 217                                              BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
 218                                              DCACHE_OFF);
 219
 220         /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
 221         addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
 222         /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
 223         addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
 224                           BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
 225                           BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
 226
 227         return 0;
 228 }
 229 #endif
 230
 231 void enable_caches(void)
 232 {
 233         dcache_enable();
 234 }
 235 #endif