arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pinctrl/machine.h>
  14
  15 #include <asm/system_misc.h>
  16 #include <asm/mach/map.h>
  17
  18 #include <mach/hardware.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91_dbgu.h>
  21 #include <mach/at91_pmc.h>
  22
  23 #include "at91_shdwc.h"
  24 #include "soc.h"
  25 #include "generic.h"
  26
  27 struct at91_init_soc __initdata at91_boot_soc;
  28
  29 struct at91_socinfo at91_soc_initdata;
  30 EXPORT_SYMBOL(at91_soc_initdata);
  31
  32 void __init at91rm9200_set_type(int type)
  33 {
  34         if (type == ARCH_REVISON_9200_PQFP)
  35                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  36         else
  37                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  38
  39         pr_info("AT91: filled in soc subtype: %s\n",
  40                 at91_get_soc_subtype(&at91_soc_initdata));
  41 }
  42
  43 void __init at91_init_irq_default(void)
  44 {
  45         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  46 }
  47
  48 void __init at91_init_interrupts(unsigned int *priority)
  49 {
  50         /* Initialize the AIC interrupt controller */
  51         at91_aic_init(priority, at91_extern_irq);
  52
  53         /* Enable GPIO interrupts */
  54         at91_gpio_irq_setup();
  55 }
  56
  57 void __iomem *at91_ramc_base[2];
  58 EXPORT_SYMBOL_GPL(at91_ramc_base);
  59
  60 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  61 {
  62         if (id < 0 || id > 1) {
  63                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  64                 BUG();
  65         }
  66         at91_ramc_base[id] = ioremap(addr, size);
  67         if (!at91_ramc_base[id])
  68                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  69 }
  70
  71 static struct map_desc sram_desc[2] __initdata;
  72
  73 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  74 {
  75         struct map_desc *desc = &sram_desc[bank];
  76
  77         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  78         if (bank > 0)
  79                 desc->virtual -= sram_desc[bank - 1].length;
  80
  81         desc->pfn = __phys_to_pfn(base);
  82         desc->length = length;
  83         desc->type = MT_DEVICE;
  84
  85         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  86                 base, length, desc->virtual);
  87
  88         iotable_init(desc, 1);
  89 }
  90
  91 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  92         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  93         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  94         .length         = SZ_16K,
  95         .type           = MT_DEVICE,
  96 };
  97
  98 static void __init soc_detect(u32 dbgu_base)
  99 {
 100         u32 cidr, socid;
 101
 102         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 103         socid = cidr & ~AT91_CIDR_VERSION;
 104
 105         switch (socid) {
 106         case ARCH_ID_AT91RM9200:
 107                 at91_soc_initdata.type = AT91_SOC_RM9200;
 108                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
 109                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 110                 at91_boot_soc = at91rm9200_soc;
 111                 break;
 112
 113         case ARCH_ID_AT91SAM9260:
 114                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 115                 at91_boot_soc = at91sam9260_soc;
 116                 break;
 117
 118         case ARCH_ID_AT91SAM9261:
 119                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 120                 at91_boot_soc = at91sam9261_soc;
 121                 break;
 122
 123         case ARCH_ID_AT91SAM9263:
 124                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 125                 at91_boot_soc = at91sam9263_soc;
 126                 break;
 127
 128         case ARCH_ID_AT91SAM9G20:
 129                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 130                 at91_boot_soc = at91sam9260_soc;
 131                 break;
 132
 133         case ARCH_ID_AT91SAM9G45:
 134                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 135                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 136                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 137                 at91_boot_soc = at91sam9g45_soc;
 138                 break;
 139
 140         case ARCH_ID_AT91SAM9RL64:
 141                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 142                 at91_boot_soc = at91sam9rl_soc;
 143                 break;
 144
 145         case ARCH_ID_AT91SAM9X5:
 146                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 147                 at91_boot_soc = at91sam9x5_soc;
 148                 break;
 149
 150         case ARCH_ID_AT91SAM9N12:
 151                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 152                 at91_boot_soc = at91sam9n12_soc;
 153                 break;
 154         }
 155
 156         /* at91sam9g10 */
 157         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 158                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 159                 at91_boot_soc = at91sam9261_soc;
 160         }
 161         /* at91sam9xe */
 162         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 163                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 164                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 165                 at91_boot_soc = at91sam9260_soc;
 166         }
 167
 168         if (!at91_soc_is_detected())
 169                 return;
 170
 171         at91_soc_initdata.cidr = cidr;
 172
 173         /* sub version of soc */
 174         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 175
 176         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 177                 switch (at91_soc_initdata.exid) {
 178                 case ARCH_EXID_AT91SAM9M10:
 179                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 180                         break;
 181                 case ARCH_EXID_AT91SAM9G46:
 182                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 183                         break;
 184                 case ARCH_EXID_AT91SAM9M11:
 185                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 186                         break;
 187                 }
 188         }
 189
 190         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 191                 switch (at91_soc_initdata.exid) {
 192                 case ARCH_EXID_AT91SAM9G15:
 193                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 194                         break;
 195                 case ARCH_EXID_AT91SAM9G35:
 196                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 197                         break;
 198                 case ARCH_EXID_AT91SAM9X35:
 199                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 200                         break;
 201                 case ARCH_EXID_AT91SAM9G25:
 202                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 203                         break;
 204                 case ARCH_EXID_AT91SAM9X25:
 205                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 206                         break;
 207                 }
 208         }
 209 }
 210
 211 static const char *soc_name[] = {
 212         [AT91_SOC_RM9200]       = "at91rm9200",
 213         [AT91_SOC_SAM9260]      = "at91sam9260",
 214         [AT91_SOC_SAM9261]      = "at91sam9261",
 215         [AT91_SOC_SAM9263]      = "at91sam9263",
 216         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 217         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 218         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 219         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 220         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 221         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 222         [AT91_SOC_NONE]         = "Unknown"
 223 };
 224
 225 const char *at91_get_soc_type(struct at91_socinfo *c)
 226 {
 227         return soc_name[c->type];
 228 }
 229 EXPORT_SYMBOL(at91_get_soc_type);
 230
 231 static const char *soc_subtype_name[] = {
 232         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 233         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 234         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 235         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 236         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 237         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 238         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 239         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 240         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 241         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 242         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 243         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 244         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 245 };
 246
 247 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 248 {
 249         return soc_subtype_name[c->subtype];
 250 }
 251 EXPORT_SYMBOL(at91_get_soc_subtype);
 252
 253 void __init at91_map_io(void)
 254 {
 255         /* Map peripherals */
 256         iotable_init(&at91_io_desc, 1);
 257
 258         at91_soc_initdata.type = AT91_SOC_NONE;
 259         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 260
 261         soc_detect(AT91_BASE_DBGU0);
 262         if (!at91_soc_is_detected())
 263                 soc_detect(AT91_BASE_DBGU1);
 264
 265         if (!at91_soc_is_detected())
 266                 panic("AT91: Impossible to detect the SOC type");
 267
 268         pr_info("AT91: Detected soc type: %s\n",
 269                 at91_get_soc_type(&at91_soc_initdata));
 270         pr_info("AT91: Detected soc subtype: %s\n",
 271                 at91_get_soc_subtype(&at91_soc_initdata));
 272
 273         if (!at91_soc_is_enabled())
 274                 panic("AT91: Soc not enabled");
 275
 276         if (at91_boot_soc.map_io)
 277                 at91_boot_soc.map_io();
 278 }
 279
 280 void __iomem *at91_shdwc_base = NULL;
 281
 282 static void at91sam9_poweroff(void)
 283 {
 284         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 285 }
 286
 287 void __init at91_ioremap_shdwc(u32 base_addr)
 288 {
 289         at91_shdwc_base = ioremap(base_addr, 16);
 290         if (!at91_shdwc_base)
 291                 panic("Impossible to ioremap at91_shdwc_base\n");
 292         pm_power_off = at91sam9_poweroff;
 293 }
 294
 295 void __iomem *at91_rstc_base;
 296
 297 void __init at91_ioremap_rstc(u32 base_addr)
 298 {
 299         at91_rstc_base = ioremap(base_addr, 16);
 300         if (!at91_rstc_base)
 301                 panic("Impossible to ioremap at91_rstc_base\n");
 302 }
 303
 304 void __iomem *at91_matrix_base;
 305 EXPORT_SYMBOL_GPL(at91_matrix_base);
 306
 307 void __init at91_ioremap_matrix(u32 base_addr)
 308 {
 309         at91_matrix_base = ioremap(base_addr, 512);
 310         if (!at91_matrix_base)
 311                 panic("Impossible to ioremap at91_matrix_base\n");
 312 }
 313
 314 #if defined(CONFIG_OF)
 315 static struct of_device_id rstc_ids[] = {
 316         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 317         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 318         { /*sentinel*/ }
 319 };
 320
 321 static void at91_dt_rstc(void)
 322 {
 323         struct device_node *np;
 324         const struct of_device_id *of_id;
 325
 326         np = of_find_matching_node(NULL, rstc_ids);
 327         if (!np)
 328                 panic("unable to find compatible rstc node in dtb\n");
 329
 330         at91_rstc_base = of_iomap(np, 0);
 331         if (!at91_rstc_base)
 332                 panic("unable to map rstc cpu registers\n");
 333
 334         of_id = of_match_node(rstc_ids, np);
 335         if (!of_id)
 336                 panic("AT91: rtsc no restart function available\n");
 337
 338         arm_pm_restart = of_id->data;
 339
 340         of_node_put(np);
 341 }
 342
 343 static struct of_device_id ramc_ids[] = {
 344         { .compatible = "atmel,at91rm9200-sdramc" },
 345         { .compatible = "atmel,at91sam9260-sdramc" },
 346         { .compatible = "atmel,at91sam9g45-ddramc" },
 347         { /*sentinel*/ }
 348 };
 349
 350 static void at91_dt_ramc(void)
 351 {
 352         struct device_node *np;
 353
 354         np = of_find_matching_node(NULL, ramc_ids);
 355         if (!np)
 356                 panic("unable to find compatible ram controller node in dtb\n");
 357
 358         at91_ramc_base[0] = of_iomap(np, 0);
 359         if (!at91_ramc_base[0])
 360                 panic("unable to map ramc[0] cpu registers\n");
 361         /* the controller may have 2 banks */
 362         at91_ramc_base[1] = of_iomap(np, 1);
 363
 364         of_node_put(np);
 365 }
 366
 367 static struct of_device_id shdwc_ids[] = {
 368         { .compatible = "atmel,at91sam9260-shdwc", },
 369         { .compatible = "atmel,at91sam9rl-shdwc", },
 370         { .compatible = "atmel,at91sam9x5-shdwc", },
 371         { /*sentinel*/ }
 372 };
 373
 374 static const char *shdwc_wakeup_modes[] = {
 375         [AT91_SHDW_WKMODE0_NONE]        = "none",
 376         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 377         [AT91_SHDW_WKMODE0_LOW]         = "low",
 378         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 379 };
 380
 381 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 382 {
 383         const char *pm;
 384         int err, i;
 385
 386         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 387         if (err < 0)
 388                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 389
 390         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 391                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 392                         return i;
 393
 394         return -ENODEV;
 395 }
 396
 397 static void at91_dt_shdwc(void)
 398 {
 399         struct device_node *np;
 400         int wakeup_mode;
 401         u32 reg;
 402         u32 mode = 0;
 403
 404         np = of_find_matching_node(NULL, shdwc_ids);
 405         if (!np) {
 406                 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
 407                 return;
 408         }
 409
 410         at91_shdwc_base = of_iomap(np, 0);
 411         if (!at91_shdwc_base)
 412                 panic("AT91: unable to map shdwc cpu registers\n");
 413
 414         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 415         if (wakeup_mode < 0) {
 416                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 417                 goto end;
 418         }
 419
 420         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 421                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 422                         pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
 423                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 424                         reg = AT91_SHDW_CPTWK0_MAX;
 425                 }
 426                 mode |= AT91_SHDW_CPTWK0_(reg);
 427         }
 428
 429         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 430                         mode |= AT91_SHDW_RTCWKEN;
 431
 432         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 433                         mode |= AT91_SHDW_RTTWKEN;
 434
 435         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 436
 437 end:
 438         pm_power_off = at91sam9_poweroff;
 439
 440         of_node_put(np);
 441 }
 442
 443 void __init at91rm9200_dt_initialize(void)
 444 {
 445         at91_dt_ramc();
 446
 447         /* Init clock subsystem */
 448         at91_dt_clock_init();
 449
 450         /* Register the processor-specific clocks */
 451         at91_boot_soc.register_clocks();
 452
 453         at91_boot_soc.init();
 454 }
 455
 456 void __init at91_dt_initialize(void)
 457 {
 458         at91_dt_rstc();
 459         at91_dt_ramc();
 460         at91_dt_shdwc();
 461
 462         /* Init clock subsystem */
 463         at91_dt_clock_init();
 464
 465         /* Register the processor-specific clocks */
 466         at91_boot_soc.register_clocks();
 467
 468         if (at91_boot_soc.init)
 469                 at91_boot_soc.init();
 470 }
 471 #endif
 472
 473 void __init at91_initialize(unsigned long main_clock)
 474 {
 475         at91_boot_soc.ioremap_registers();
 476
 477         /* Init clock subsystem */
 478         at91_clock_init(main_clock);
 479
 480         /* Register the processor-specific clocks */
 481         at91_boot_soc.register_clocks();
 482
 483         at91_boot_soc.init();
 484
 485         pinctrl_provide_dummies();
 486 }