2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <linux/module.h>
13 #include <asm/mach/map.h>
15 #include <mach/hardware.h>
17 #include <mach/at91_dbgu.h>
18 #include <mach/at91_pmc.h>
19 #include <mach/at91_shdwc.h>
24 struct at91_init_soc __initdata at91_boot_soc;
26 struct at91_socinfo at91_soc_initdata;
27 EXPORT_SYMBOL(at91_soc_initdata);
29 void __init at91rm9200_set_type(int type)
31 if (type == ARCH_REVISON_9200_PQFP)
32 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
36 pr_info("AT91: filled in soc subtype: %s\n",
37 at91_get_soc_subtype(&at91_soc_initdata));
40 void __init at91_init_irq_default(void)
42 at91_init_interrupts(at91_boot_soc.default_irq_priority);
45 void __init at91_init_interrupts(unsigned int *priority)
47 /* Initialize the AIC interrupt controller */
48 at91_aic_init(priority);
50 /* Enable GPIO interrupts */
51 at91_gpio_irq_setup();
54 static struct map_desc sram_desc[2] __initdata;
56 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
58 struct map_desc *desc = &sram_desc[bank];
60 desc->virtual = AT91_IO_VIRT_BASE - length;
62 desc->virtual -= sram_desc[bank - 1].length;
64 desc->pfn = __phys_to_pfn(base);
65 desc->length = length;
66 desc->type = MT_DEVICE;
68 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
69 base, length, desc->virtual);
71 iotable_init(desc, 1);
74 static struct map_desc at91_io_desc __initdata = {
75 .virtual = AT91_VA_BASE_SYS,
76 .pfn = __phys_to_pfn(AT91_BASE_SYS),
81 static void __init soc_detect(u32 dbgu_base)
85 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
86 socid = cidr & ~AT91_CIDR_VERSION;
89 case ARCH_ID_AT91RM9200:
90 at91_soc_initdata.type = AT91_SOC_RM9200;
91 at91_boot_soc = at91rm9200_soc;
94 case ARCH_ID_AT91SAM9260:
95 at91_soc_initdata.type = AT91_SOC_SAM9260;
96 at91_boot_soc = at91sam9260_soc;
99 case ARCH_ID_AT91SAM9261:
100 at91_soc_initdata.type = AT91_SOC_SAM9261;
101 at91_boot_soc = at91sam9261_soc;
104 case ARCH_ID_AT91SAM9263:
105 at91_soc_initdata.type = AT91_SOC_SAM9263;
106 at91_boot_soc = at91sam9263_soc;
109 case ARCH_ID_AT91SAM9G20:
110 at91_soc_initdata.type = AT91_SOC_SAM9G20;
111 at91_boot_soc = at91sam9260_soc;
114 case ARCH_ID_AT91SAM9G45:
115 at91_soc_initdata.type = AT91_SOC_SAM9G45;
116 if (cidr == ARCH_ID_AT91SAM9G45ES)
117 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
118 at91_boot_soc = at91sam9g45_soc;
121 case ARCH_ID_AT91SAM9RL64:
122 at91_soc_initdata.type = AT91_SOC_SAM9RL;
123 at91_boot_soc = at91sam9rl_soc;
126 case ARCH_ID_AT91SAM9X5:
127 at91_soc_initdata.type = AT91_SOC_SAM9X5;
128 at91_boot_soc = at91sam9x5_soc;
133 if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
134 at91_soc_initdata.type = AT91_SOC_SAM9G10;
135 at91_boot_soc = at91sam9261_soc;
138 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
139 at91_soc_initdata.type = AT91_SOC_SAM9260;
140 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
141 at91_boot_soc = at91sam9260_soc;
144 if (!at91_soc_is_detected())
147 at91_soc_initdata.cidr = cidr;
149 /* sub version of soc */
150 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
152 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
153 switch (at91_soc_initdata.exid) {
154 case ARCH_EXID_AT91SAM9M10:
155 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
157 case ARCH_EXID_AT91SAM9G46:
158 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
160 case ARCH_EXID_AT91SAM9M11:
161 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
166 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
167 switch (at91_soc_initdata.exid) {
168 case ARCH_EXID_AT91SAM9G15:
169 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
171 case ARCH_EXID_AT91SAM9G35:
172 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
174 case ARCH_EXID_AT91SAM9X35:
175 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
177 case ARCH_EXID_AT91SAM9G25:
178 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
180 case ARCH_EXID_AT91SAM9X25:
181 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
187 static const char *soc_name[] = {
188 [AT91_SOC_RM9200] = "at91rm9200",
189 [AT91_SOC_SAM9260] = "at91sam9260",
190 [AT91_SOC_SAM9261] = "at91sam9261",
191 [AT91_SOC_SAM9263] = "at91sam9263",
192 [AT91_SOC_SAM9G10] = "at91sam9g10",
193 [AT91_SOC_SAM9G20] = "at91sam9g20",
194 [AT91_SOC_SAM9G45] = "at91sam9g45",
195 [AT91_SOC_SAM9RL] = "at91sam9rl",
196 [AT91_SOC_SAM9X5] = "at91sam9x5",
197 [AT91_SOC_NONE] = "Unknown"
200 const char *at91_get_soc_type(struct at91_socinfo *c)
202 return soc_name[c->type];
204 EXPORT_SYMBOL(at91_get_soc_type);
206 static const char *soc_subtype_name[] = {
207 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
208 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
209 [AT91_SOC_SAM9XE] = "at91sam9xe",
210 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
211 [AT91_SOC_SAM9M10] = "at91sam9m10",
212 [AT91_SOC_SAM9G46] = "at91sam9g46",
213 [AT91_SOC_SAM9M11] = "at91sam9m11",
214 [AT91_SOC_SAM9G15] = "at91sam9g15",
215 [AT91_SOC_SAM9G35] = "at91sam9g35",
216 [AT91_SOC_SAM9X35] = "at91sam9x35",
217 [AT91_SOC_SAM9G25] = "at91sam9g25",
218 [AT91_SOC_SAM9X25] = "at91sam9x25",
219 [AT91_SOC_SUBTYPE_NONE] = "Unknown"
222 const char *at91_get_soc_subtype(struct at91_socinfo *c)
224 return soc_subtype_name[c->subtype];
226 EXPORT_SYMBOL(at91_get_soc_subtype);
228 void __init at91_map_io(void)
230 /* Map peripherals */
231 iotable_init(&at91_io_desc, 1);
233 at91_soc_initdata.type = AT91_SOC_NONE;
234 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
236 soc_detect(AT91_BASE_DBGU0);
237 if (!at91_soc_is_detected())
238 soc_detect(AT91_BASE_DBGU1);
240 if (!at91_soc_is_detected())
241 panic("AT91: Impossible to detect the SOC type");
243 pr_info("AT91: Detected soc type: %s\n",
244 at91_get_soc_type(&at91_soc_initdata));
245 pr_info("AT91: Detected soc subtype: %s\n",
246 at91_get_soc_subtype(&at91_soc_initdata));
248 if (!at91_soc_is_enabled())
249 panic("AT91: Soc not enabled");
251 if (at91_boot_soc.map_io)
252 at91_boot_soc.map_io();
255 void __iomem *at91_shdwc_base = NULL;
257 static void at91sam9_poweroff(void)
259 at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
262 void __init at91_ioremap_shdwc(u32 base_addr)
264 at91_shdwc_base = ioremap(base_addr, 16);
265 if (!at91_shdwc_base)
266 panic("Impossible to ioremap at91_shdwc_base\n");
267 pm_power_off = at91sam9_poweroff;
270 void __iomem *at91_rstc_base;
272 void __init at91_ioremap_rstc(u32 base_addr)
274 at91_rstc_base = ioremap(base_addr, 16);
276 panic("Impossible to ioremap at91_rstc_base\n");
279 void __iomem *at91_matrix_base;
281 void __init at91_ioremap_matrix(u32 base_addr)
283 at91_matrix_base = ioremap(base_addr, 512);
284 if (!at91_matrix_base)
285 panic("Impossible to ioremap at91_matrix_base\n");
288 void __init at91_initialize(unsigned long main_clock)
290 at91_boot_soc.ioremap_registers();
292 /* Init clock subsystem */
293 at91_clock_init(main_clock);
295 /* Register the processor-specific clocks */
296 at91_boot_soc.register_clocks();
298 at91_boot_soc.init();