arch/arm/mach-at91/pm_suspend.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/mach-at91/pm_slow_clock.S
   4  *
   5  *  Copyright (C) 2006 Savin Zlobec
   6  *
   7  * AT91SAM9 support:
   8  *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
   9  */
  10 #include <linux/linkage.h>
  11 #include <linux/clk/at91_pmc.h>
  12 #include "pm.h"
  13 #include "pm_data-offsets.h"
  14
  15 #define SRAMC_SELF_FRESH_ACTIVE         0x01
  16 #define SRAMC_SELF_FRESH_EXIT           0x00
  17
  18 pmc     .req    r0
  19 tmp1    .req    r4
  20 tmp2    .req    r5
  21 tmp3    .req    r6
  22
  23 /*
  24  * Wait until master clock is ready (after switching master clock source)
  25  *
  26  * @r_mckid:    register holding master clock identifier
  27  *
  28  * Side effects: overwrites r7, r8
  29  */
  30         .macro wait_mckrdy r_mckid
  31 #ifdef CONFIG_SOC_SAMA7
  32         cmp     \r_mckid, #0
  33         beq     1f
  34         mov     r7, #AT91_PMC_MCKXRDY
  35         b       2f
  36 #endif
  37 1:      mov     r7, #AT91_PMC_MCKRDY
  38 2:      ldr     r8, [pmc, #AT91_PMC_SR]
  39         and     r8, r7
  40         cmp     r8, r7
  41         bne     2b
  42         .endm
  43
  44 /*
  45  * Wait until master oscillator has stabilized.
  46  *
  47  * Side effects: overwrites r7
  48  */
  49         .macro wait_moscrdy
  50 1:      ldr     r7, [pmc, #AT91_PMC_SR]
  51         tst     r7, #AT91_PMC_MOSCS
  52         beq     1b
  53         .endm
  54
  55 /*
  56  * Wait for main oscillator selection is done
  57  *
  58  * Side effects: overwrites r7
  59  */
  60         .macro wait_moscsels
  61 1:      ldr     r7, [pmc, #AT91_PMC_SR]
  62         tst     r7, #AT91_PMC_MOSCSELS
  63         beq     1b
  64         .endm
  65
  66 /*
  67  * Put the processor to enter the idle state
  68  *
  69  * Side effects: overwrites r7
  70  */
  71         .macro at91_cpu_idle
  72
  73 #if defined(CONFIG_CPU_V7)
  74         mov     r7, #AT91_PMC_PCK
  75         str     r7, [pmc, #AT91_PMC_SCDR]
  76
  77         dsb
  78
  79         wfi             @ Wait For Interrupt
  80 #else
  81         mcr     p15, 0, tmp1, c7, c0, 4
  82 #endif
  83
  84         .endm
  85
  86 /**
  87  * Set state for 2.5V low power regulator
  88  * @ena: 0 - disable regulator
  89  *       1 - enable regulator
  90  *
  91  * Side effects: overwrites r7, r8, r9, r10
  92  */
  93         .macro at91_2_5V_reg_set_low_power ena
  94 #ifdef CONFIG_SOC_SAMA7
  95         ldr     r7, .sfrbu
  96         mov     r8, #\ena
  97         ldr     r9, [r7, #AT91_SFRBU_25LDOCR]
  98         orr     r9, r9, #AT91_SFRBU_25LDOCR_LP
  99         cmp     r8, #1
 100         beq     lp_done_\ena
 101         bic     r9, r9, #AT91_SFRBU_25LDOCR_LP
 102 lp_done_\ena:
 103         ldr     r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
 104         orr     r9, r9, r10
 105         str     r9, [r7, #AT91_SFRBU_25LDOCR]
 106 #endif
 107         .endm
 108
 109         .macro at91_backup_set_lpm reg
 110 #ifdef CONFIG_SOC_SAMA7
 111         orr     \reg, \reg, #0x200000
 112 #endif
 113         .endm
 114
 115         .text
 116
 117         .arm
 118
 119 #ifdef CONFIG_SOC_SAMA7
 120 /**
 121  * Enable self-refresh
 122  *
 123  * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
 124  */
 125 .macro at91_sramc_self_refresh_ena
 126         ldr     r2, .sramc_base
 127         ldr     r3, .sramc_phy_base
 128         ldr     r7, .pm_mode
 129
 130         dsb
 131
 132         /* Disable all AXI ports. */
 133         ldr     tmp1, [r2, #UDDRC_PCTRL_0]
 134         bic     tmp1, tmp1, #0x1
 135         str     tmp1, [r2, #UDDRC_PCTRL_0]
 136
 137         ldr     tmp1, [r2, #UDDRC_PCTRL_1]
 138         bic     tmp1, tmp1, #0x1
 139         str     tmp1, [r2, #UDDRC_PCTRL_1]
 140
 141         ldr     tmp1, [r2, #UDDRC_PCTRL_2]
 142         bic     tmp1, tmp1, #0x1
 143         str     tmp1, [r2, #UDDRC_PCTRL_2]
 144
 145         ldr     tmp1, [r2, #UDDRC_PCTRL_3]
 146         bic     tmp1, tmp1, #0x1
 147         str     tmp1, [r2, #UDDRC_PCTRL_3]
 148
 149         ldr     tmp1, [r2, #UDDRC_PCTRL_4]
 150         bic     tmp1, tmp1, #0x1
 151         str     tmp1, [r2, #UDDRC_PCTRL_4]
 152
 153 sr_ena_1:
 154         /* Wait for all ports to disable. */
 155         ldr     tmp1, [r2, #UDDRC_PSTAT]
 156         ldr     tmp2, =UDDRC_PSTAT_ALL_PORTS
 157         tst     tmp1, tmp2
 158         bne     sr_ena_1
 159
 160         /* Switch to self-refresh. */
 161         ldr     tmp1, [r2, #UDDRC_PWRCTL]
 162         orr     tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
 163         str     tmp1, [r2, #UDDRC_PWRCTL]
 164
 165 sr_ena_2:
 166         /* Wait for self-refresh enter. */
 167         ldr     tmp1, [r2, #UDDRC_STAT]
 168         bic     tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
 169         cmp     tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
 170         bne     sr_ena_2
 171
 172         /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
 173         cmp     r7, #AT91_PM_BACKUP
 174         beq     sr_ena_3
 175         ldr     tmp1, [r3, #DDR3PHY_PIR]
 176         orr     tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
 177         str     tmp1, [r3, #DDR3PHY_PIR]
 178
 179 sr_ena_3:
 180         /* Power down DDR PHY data receivers. */
 181         ldr     tmp1, [r3, #DDR3PHY_DXCCR]
 182         orr     tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
 183         str     tmp1, [r3, #DDR3PHY_DXCCR]
 184
 185         /* Power down ADDR/CMD IO. */
 186         ldr     tmp1, [r3, #DDR3PHY_ACIOCR]
 187         orr     tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
 188         orr     tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
 189         orr     tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
 190         str     tmp1, [r3, #DDR3PHY_ACIOCR]
 191
 192         /* Power down ODT. */
 193         ldr     tmp1, [r3, #DDR3PHY_DSGCR]
 194         orr     tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
 195         str     tmp1, [r3, #DDR3PHY_DSGCR]
 196 .endm
 197
 198 /**
 199  * Disable self-refresh
 200  *
 201  * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
 202  */
 203 .macro at91_sramc_self_refresh_dis
 204         ldr     r2, .sramc_base
 205         ldr     r3, .sramc_phy_base
 206
 207         /* Power up DDR PHY data receivers. */
 208         ldr     tmp1, [r3, #DDR3PHY_DXCCR]
 209         bic     tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
 210         str     tmp1, [r3, #DDR3PHY_DXCCR]
 211
 212         /* Power up the output of CK and CS pins. */
 213         ldr     tmp1, [r3, #DDR3PHY_ACIOCR]
 214         bic     tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
 215         bic     tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
 216         bic     tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
 217         str     tmp1, [r3, #DDR3PHY_ACIOCR]
 218
 219         /* Power up ODT. */
 220         ldr     tmp1, [r3, #DDR3PHY_DSGCR]
 221         bic     tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
 222         str     tmp1, [r3, #DDR3PHY_DSGCR]
 223
 224         /* Take DDR PHY's DLL out of bypass mode. */
 225         ldr     tmp1, [r3, #DDR3PHY_PIR]
 226         bic     tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
 227         str     tmp1, [r3, #DDR3PHY_PIR]
 228
 229         /* Enable quasi-dynamic programming. */
 230         mov     tmp1, #0
 231         str     tmp1, [r2, #UDDRC_SWCTRL]
 232
 233         /* De-assert SDRAM initialization. */
 234         ldr     tmp1, [r2, #UDDRC_DFIMISC]
 235         bic     tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
 236         str     tmp1, [r2, #UDDRC_DFIMISC]
 237
 238         /* Quasi-dynamic programming done. */
 239         mov     tmp1, #UDDRC_SWCTRL_SW_DONE
 240         str     tmp1, [r2, #UDDRC_SWCTRL]
 241
 242 sr_dis_1:
 243         ldr     tmp1, [r2, #UDDRC_SWSTAT]
 244         tst     tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
 245         beq     sr_dis_1
 246
 247         /* DLL soft-reset + DLL lock wait + ITM reset */
 248         mov     tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
 249                         DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
 250         str     tmp1, [r3, #DDR3PHY_PIR]
 251
 252 sr_dis_4:
 253         /* Wait for it. */
 254         ldr     tmp1, [r3, #DDR3PHY_PGSR]
 255         tst     tmp1, #DDR3PHY_PGSR_IDONE
 256         beq     sr_dis_4
 257
 258         /* Enable quasi-dynamic programming. */
 259         mov     tmp1, #0
 260         str     tmp1, [r2, #UDDRC_SWCTRL]
 261
 262         /* Assert PHY init complete enable signal. */
 263         ldr     tmp1, [r2, #UDDRC_DFIMISC]
 264         orr     tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
 265         str     tmp1, [r2, #UDDRC_DFIMISC]
 266
 267         /* Programming is done. Set sw_done. */
 268         mov     tmp1, #UDDRC_SWCTRL_SW_DONE
 269         str     tmp1, [r2, #UDDRC_SWCTRL]
 270
 271 sr_dis_5:
 272         /* Wait for it. */
 273         ldr     tmp1, [r2, #UDDRC_SWSTAT]
 274         tst     tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
 275         beq     sr_dis_5
 276
 277         /* Trigger self-refresh exit. */
 278         ldr     tmp1, [r2, #UDDRC_PWRCTL]
 279         bic     tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
 280         str     tmp1, [r2, #UDDRC_PWRCTL]
 281
 282 sr_dis_6:
 283         /* Wait for self-refresh exit done. */
 284         ldr     tmp1, [r2, #UDDRC_STAT]
 285         bic     tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
 286         cmp     tmp1, #UDDRC_STAT_OPMODE_NORMAL
 287         bne     sr_dis_6
 288
 289         /* Enable all AXI ports. */
 290         ldr     tmp1, [r2, #UDDRC_PCTRL_0]
 291         orr     tmp1, tmp1, #0x1
 292         str     tmp1, [r2, #UDDRC_PCTRL_0]
 293
 294         ldr     tmp1, [r2, #UDDRC_PCTRL_1]
 295         orr     tmp1, tmp1, #0x1
 296         str     tmp1, [r2, #UDDRC_PCTRL_1]
 297
 298         ldr     tmp1, [r2, #UDDRC_PCTRL_2]
 299         orr     tmp1, tmp1, #0x1
 300         str     tmp1, [r2, #UDDRC_PCTRL_2]
 301
 302         ldr     tmp1, [r2, #UDDRC_PCTRL_3]
 303         orr     tmp1, tmp1, #0x1
 304         str     tmp1, [r2, #UDDRC_PCTRL_3]
 305
 306         ldr     tmp1, [r2, #UDDRC_PCTRL_4]
 307         orr     tmp1, tmp1, #0x1
 308         str     tmp1, [r2, #UDDRC_PCTRL_4]
 309
 310         dsb
 311 .endm
 312 #else
 313 /**
 314  * Enable self-refresh
 315  *
 316  * register usage:
 317  *      @r1: memory type
 318  *      @r2: base address of the sram controller
 319  *      @r3: temporary
 320  */
 321 .macro at91_sramc_self_refresh_ena
 322         ldr     r1, .memtype
 323         ldr     r2, .sramc_base
 324
 325         cmp     r1, #AT91_MEMCTRL_MC
 326         bne     sr_ena_ddrc_sf
 327
 328         /* Active SDRAM self-refresh mode */
 329         mov     r3, #1
 330         str     r3, [r2, #AT91_MC_SDRAMC_SRR]
 331         b       sr_ena_exit
 332
 333 sr_ena_ddrc_sf:
 334         cmp     r1, #AT91_MEMCTRL_DDRSDR
 335         bne     sr_ena_sdramc_sf
 336
 337         /*
 338          * DDR Memory controller
 339          */
 340
 341         /* LPDDR1 --> force DDR2 mode during self-refresh */
 342         ldr     r3, [r2, #AT91_DDRSDRC_MDR]
 343         str     r3, .saved_sam9_mdr
 344         bic     r3, r3, #~AT91_DDRSDRC_MD
 345         cmp     r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
 346         ldreq   r3, [r2, #AT91_DDRSDRC_MDR]
 347         biceq   r3, r3, #AT91_DDRSDRC_MD
 348         orreq   r3, r3, #AT91_DDRSDRC_MD_DDR2
 349         streq   r3, [r2, #AT91_DDRSDRC_MDR]
 350
 351         /* Active DDRC self-refresh mode */
 352         ldr     r3, [r2, #AT91_DDRSDRC_LPR]
 353         str     r3, .saved_sam9_lpr
 354         bic     r3, r3, #AT91_DDRSDRC_LPCB
 355         orr     r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 356         str     r3, [r2, #AT91_DDRSDRC_LPR]
 357
 358         /* If using the 2nd ddr controller */
 359         ldr     r2, .sramc1_base
 360         cmp     r2, #0
 361         beq     sr_ena_no_2nd_ddrc
 362
 363         ldr     r3, [r2, #AT91_DDRSDRC_MDR]
 364         str     r3, .saved_sam9_mdr1
 365         bic     r3, r3, #~AT91_DDRSDRC_MD
 366         cmp     r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
 367         ldreq   r3, [r2, #AT91_DDRSDRC_MDR]
 368         biceq   r3, r3, #AT91_DDRSDRC_MD
 369         orreq   r3, r3, #AT91_DDRSDRC_MD_DDR2
 370         streq   r3, [r2, #AT91_DDRSDRC_MDR]
 371
 372         /* Active DDRC self-refresh mode */
 373         ldr     r3, [r2, #AT91_DDRSDRC_LPR]
 374         str     r3, .saved_sam9_lpr1
 375         bic     r3, r3, #AT91_DDRSDRC_LPCB
 376         orr     r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 377         str     r3, [r2, #AT91_DDRSDRC_LPR]
 378
 379 sr_ena_no_2nd_ddrc:
 380         b       sr_ena_exit
 381
 382         /*
 383          * SDRAMC Memory controller
 384          */
 385 sr_ena_sdramc_sf:
 386         /* Active SDRAMC self-refresh mode */
 387         ldr     r3, [r2, #AT91_SDRAMC_LPR]
 388         str     r3, .saved_sam9_lpr
 389         bic     r3, r3, #AT91_SDRAMC_LPCB
 390         orr     r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
 391         str     r3, [r2, #AT91_SDRAMC_LPR]
 392
 393         ldr     r3, .saved_sam9_lpr
 394         str     r3, [r2, #AT91_SDRAMC_LPR]
 395
 396 sr_ena_exit:
 397 .endm
 398
 399 /**
 400  * Disable self-refresh
 401  *
 402  * register usage:
 403  *      @r1: memory type
 404  *      @r2: base address of the sram controller
 405  *      @r3: temporary
 406  */
 407 .macro at91_sramc_self_refresh_dis
 408         ldr     r1, .memtype
 409         ldr     r2, .sramc_base
 410
 411         cmp     r1, #AT91_MEMCTRL_MC
 412         bne     sr_dis_ddrc_exit_sf
 413
 414         /*
 415          * at91rm9200 Memory controller
 416          */
 417
 418          /*
 419           * For exiting the self-refresh mode, do nothing,
 420           * automatically exit the self-refresh mode.
 421           */
 422         b       sr_dis_exit
 423
 424 sr_dis_ddrc_exit_sf:
 425         cmp     r1, #AT91_MEMCTRL_DDRSDR
 426         bne     sdramc_exit_sf
 427
 428         /* DDR Memory controller */
 429
 430         /* Restore MDR in case of LPDDR1 */
 431         ldr     r3, .saved_sam9_mdr
 432         str     r3, [r2, #AT91_DDRSDRC_MDR]
 433         /* Restore LPR on AT91 with DDRAM */
 434         ldr     r3, .saved_sam9_lpr
 435         str     r3, [r2, #AT91_DDRSDRC_LPR]
 436
 437         /* If using the 2nd ddr controller */
 438         ldr     r2, .sramc1_base
 439         cmp     r2, #0
 440         ldrne   r3, .saved_sam9_mdr1
 441         strne   r3, [r2, #AT91_DDRSDRC_MDR]
 442         ldrne   r3, .saved_sam9_lpr1
 443         strne   r3, [r2, #AT91_DDRSDRC_LPR]
 444
 445         b       sr_dis_exit
 446
 447 sdramc_exit_sf:
 448         /* SDRAMC Memory controller */
 449         ldr     r3, .saved_sam9_lpr
 450         str     r3, [r2, #AT91_SDRAMC_LPR]
 451
 452 sr_dis_exit:
 453 .endm
 454 #endif
 455
 456 .macro at91_pm_ulp0_mode
 457         ldr     pmc, .pmc_base
 458         ldr     tmp2, .pm_mode
 459         ldr     tmp3, .mckr_offset
 460
 461         /* Check if ULP0 fast variant has been requested. */
 462         cmp     tmp2, #AT91_PM_ULP0_FAST
 463         bne     0f
 464
 465         /* Set highest prescaler for power saving */
 466         ldr     tmp1, [pmc, tmp3]
 467         bic     tmp1, tmp1, #AT91_PMC_PRES
 468         orr     tmp1, tmp1, #AT91_PMC_PRES_64
 469         str     tmp1, [pmc, tmp3]
 470
 471         mov     tmp3, #0
 472         wait_mckrdy tmp3
 473         b       1f
 474
 475 0:
 476         /* Turn off the crystal oscillator */
 477         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 478         bic     tmp1, tmp1, #AT91_PMC_MOSCEN
 479         orr     tmp1, tmp1, #AT91_PMC_KEY
 480         str     tmp1, [pmc, #AT91_CKGR_MOR]
 481
 482         /* Save RC oscillator state */
 483         ldr     tmp1, [pmc, #AT91_PMC_SR]
 484         str     tmp1, .saved_osc_status
 485         tst     tmp1, #AT91_PMC_MOSCRCS
 486         bne     1f
 487
 488         /* Turn off RC oscillator */
 489         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 490         bic     tmp1, tmp1, #AT91_PMC_MOSCRCEN
 491         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 492         orr     tmp1, tmp1, #AT91_PMC_KEY
 493         str     tmp1, [pmc, #AT91_CKGR_MOR]
 494
 495         /* Wait main RC disabled done */
 496 2:      ldr     tmp1, [pmc, #AT91_PMC_SR]
 497         tst     tmp1, #AT91_PMC_MOSCRCS
 498         bne     2b
 499
 500         /* Wait for interrupt */
 501 1:      at91_cpu_idle
 502
 503         /* Check if ULP0 fast variant has been requested. */
 504         cmp     tmp2, #AT91_PM_ULP0_FAST
 505         bne     5f
 506
 507         /* Set lowest prescaler for fast resume. */
 508         ldr     tmp3, .mckr_offset
 509         ldr     tmp1, [pmc, tmp3]
 510         bic     tmp1, tmp1, #AT91_PMC_PRES
 511         str     tmp1, [pmc, tmp3]
 512
 513         mov     tmp3, #0
 514         wait_mckrdy tmp3
 515         b       6f
 516
 517 5:      /* Restore RC oscillator state */
 518         ldr     tmp1, .saved_osc_status
 519         tst     tmp1, #AT91_PMC_MOSCRCS
 520         beq     4f
 521
 522         /* Turn on RC oscillator */
 523         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 524         orr     tmp1, tmp1, #AT91_PMC_MOSCRCEN
 525         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 526         orr     tmp1, tmp1, #AT91_PMC_KEY
 527         str     tmp1, [pmc, #AT91_CKGR_MOR]
 528
 529         /* Wait main RC stabilization */
 530 3:      ldr     tmp1, [pmc, #AT91_PMC_SR]
 531         tst     tmp1, #AT91_PMC_MOSCRCS
 532         beq     3b
 533
 534         /* Turn on the crystal oscillator */
 535 4:      ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 536         orr     tmp1, tmp1, #AT91_PMC_MOSCEN
 537         orr     tmp1, tmp1, #AT91_PMC_KEY
 538         str     tmp1, [pmc, #AT91_CKGR_MOR]
 539
 540         wait_moscrdy
 541 6:
 542 .endm
 543
 544 /**
 545  * Note: This procedure only applies on the platform which uses
 546  * the external crystal oscillator as a main clock source.
 547  */
 548 .macro at91_pm_ulp1_mode
 549         ldr     pmc, .pmc_base
 550         ldr     tmp2, .mckr_offset
 551         mov     tmp3, #0
 552
 553         /* Save RC oscillator state and check if it is enabled. */
 554         ldr     tmp1, [pmc, #AT91_PMC_SR]
 555         str     tmp1, .saved_osc_status
 556         tst     tmp1, #AT91_PMC_MOSCRCS
 557         bne     2f
 558
 559         /* Enable RC oscillator */
 560         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 561         orr     tmp1, tmp1, #AT91_PMC_MOSCRCEN
 562         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 563         orr     tmp1, tmp1, #AT91_PMC_KEY
 564         str     tmp1, [pmc, #AT91_CKGR_MOR]
 565
 566         /* Wait main RC stabilization */
 567 1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
 568         tst     tmp1, #AT91_PMC_MOSCRCS
 569         beq     1b
 570
 571         /* Switch the main clock source to 12-MHz RC oscillator */
 572 2:      ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 573         bic     tmp1, tmp1, #AT91_PMC_MOSCSEL
 574         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 575         orr     tmp1, tmp1, #AT91_PMC_KEY
 576         str     tmp1, [pmc, #AT91_CKGR_MOR]
 577
 578         wait_moscsels
 579
 580         /* Disable the crystal oscillator */
 581         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 582         bic     tmp1, tmp1, #AT91_PMC_MOSCEN
 583         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 584         orr     tmp1, tmp1, #AT91_PMC_KEY
 585         str     tmp1, [pmc, #AT91_CKGR_MOR]
 586
 587         /* Switch the master clock source to main clock */
 588         ldr     tmp1, [pmc, tmp2]
 589         bic     tmp1, tmp1, #AT91_PMC_CSS
 590         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
 591         str     tmp1, [pmc, tmp2]
 592
 593         wait_mckrdy tmp3
 594
 595         /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
 596         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 597         orr     tmp1, tmp1, #AT91_PMC_WAITMODE
 598         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 599         orr     tmp1, tmp1, #AT91_PMC_KEY
 600         str     tmp1, [pmc, #AT91_CKGR_MOR]
 601
 602         /* Quirk for SAM9X60's PMC */
 603         nop
 604         nop
 605
 606         wait_mckrdy tmp3
 607
 608         /* Enable the crystal oscillator */
 609         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 610         orr     tmp1, tmp1, #AT91_PMC_MOSCEN
 611         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 612         orr     tmp1, tmp1, #AT91_PMC_KEY
 613         str     tmp1, [pmc, #AT91_CKGR_MOR]
 614
 615         wait_moscrdy
 616
 617         /* Switch the master clock source to slow clock */
 618         ldr     tmp1, [pmc, tmp2]
 619         bic     tmp1, tmp1, #AT91_PMC_CSS
 620         str     tmp1, [pmc, tmp2]
 621
 622         wait_mckrdy tmp3
 623
 624         /* Switch main clock source to crystal oscillator */
 625         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 626         orr     tmp1, tmp1, #AT91_PMC_MOSCSEL
 627         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 628         orr     tmp1, tmp1, #AT91_PMC_KEY
 629         str     tmp1, [pmc, #AT91_CKGR_MOR]
 630
 631         wait_moscsels
 632
 633         /* Switch the master clock source to main clock */
 634         ldr     tmp1, [pmc, tmp2]
 635         bic     tmp1, tmp1, #AT91_PMC_CSS
 636         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
 637         str     tmp1, [pmc, tmp2]
 638
 639         wait_mckrdy tmp3
 640
 641         /* Restore RC oscillator state */
 642         ldr     tmp1, .saved_osc_status
 643         tst     tmp1, #AT91_PMC_MOSCRCS
 644         bne     3f
 645
 646         /* Disable RC oscillator */
 647         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 648         bic     tmp1, tmp1, #AT91_PMC_MOSCRCEN
 649         bic     tmp1, tmp1, #AT91_PMC_KEY_MASK
 650         orr     tmp1, tmp1, #AT91_PMC_KEY
 651         str     tmp1, [pmc, #AT91_CKGR_MOR]
 652
 653         /* Wait RC oscillator disable done */
 654 4:      ldr     tmp1, [pmc, #AT91_PMC_SR]
 655         tst     tmp1, #AT91_PMC_MOSCRCS
 656         bne     4b
 657
 658 3:
 659 .endm
 660
 661 .macro at91_plla_disable
 662         /* Save PLLA setting and disable it */
 663         ldr     tmp1, .pmc_version
 664         cmp     tmp1, #AT91_PMC_V1
 665         beq     1f
 666
 667 #ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
 668         /* Save PLLA settings. */
 669         ldr     tmp2, [pmc, #AT91_PMC_PLL_UPDT]
 670         bic     tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
 671         str     tmp2, [pmc, #AT91_PMC_PLL_UPDT]
 672
 673         /* save div. */
 674         mov     tmp1, #0
 675         ldr     tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
 676         bic     tmp2, tmp2, #0xffffff00
 677         orr     tmp1, tmp1, tmp2
 678
 679         /* save mul. */
 680         ldr     tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
 681         bic     tmp2, tmp2, #0xffffff
 682         orr     tmp1, tmp1, tmp2
 683         str     tmp1, .saved_pllar
 684
 685         /* step 2. */
 686         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 687         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 688         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 689         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 690
 691         /* step 3. */
 692         ldr     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 693         bic     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
 694         orr     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
 695         str     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 696
 697         /* step 4. */
 698         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 699         orr     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 700         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 701         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 702
 703         /* step 5. */
 704         ldr     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 705         bic     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
 706         str     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 707
 708         /* step 7. */
 709         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 710         orr     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 711         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 712         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 713
 714         b       2f
 715 #endif
 716
 717 1:      /* Save PLLA setting and disable it */
 718         ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
 719         str     tmp1, .saved_pllar
 720
 721         /* Disable PLLA. */
 722         mov     tmp1, #AT91_PMC_PLLCOUNT
 723         orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
 724         str     tmp1, [pmc, #AT91_CKGR_PLLAR]
 725 2:
 726 .endm
 727
 728 .macro at91_plla_enable
 729         ldr     tmp2, .saved_pllar
 730         ldr     tmp3, .pmc_version
 731         cmp     tmp3, #AT91_PMC_V1
 732         beq     4f
 733
 734 #ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
 735         /* step 1. */
 736         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 737         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 738         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 739         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 740
 741         /* step 2. */
 742         ldr     tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
 743         str     tmp1, [pmc, #AT91_PMC_PLL_ACR]
 744
 745         /* step 3. */
 746         ldr     tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
 747         mov     tmp3, tmp2
 748         bic     tmp3, tmp3, #0xffffff
 749         orr     tmp1, tmp1, tmp3
 750         str     tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
 751
 752         /* step 8. */
 753         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 754         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 755         orr     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 756         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 757
 758         /* step 9. */
 759         ldr     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 760         orr     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
 761         orr     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
 762         orr     tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
 763         bic     tmp1, tmp1, #0xff
 764         mov     tmp3, tmp2
 765         bic     tmp3, tmp3, #0xffffff00
 766         orr     tmp1, tmp1, tmp3
 767         str     tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
 768
 769         /* step 10. */
 770         ldr     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 771         orr     tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
 772         bic     tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
 773         str     tmp1, [pmc, #AT91_PMC_PLL_UPDT]
 774
 775         /* step 11. */
 776 3:      ldr     tmp1, [pmc, #AT91_PMC_PLL_ISR0]
 777         tst     tmp1, #0x1
 778         beq     3b
 779         b       2f
 780 #endif
 781
 782         /* Restore PLLA setting */
 783 4:      str     tmp2, [pmc, #AT91_CKGR_PLLAR]
 784
 785         /* Enable PLLA. */
 786         tst     tmp2, #(AT91_PMC_MUL &  0xff0000)
 787         bne     1f
 788         tst     tmp2, #(AT91_PMC_MUL & ~0xff0000)
 789         beq     2f
 790
 791 1:      ldr     tmp1, [pmc, #AT91_PMC_SR]
 792         tst     tmp1, #AT91_PMC_LOCKA
 793         beq     1b
 794 2:
 795 .endm
 796
 797 /**
 798  * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock
 799  *
 800  * Side effects: overwrites tmp1, tmp2
 801  */
 802 .macro at91_mckx_ps_enable
 803 #ifdef CONFIG_SOC_SAMA7
 804         ldr     pmc, .pmc_base
 805
 806         /* There are 4 MCKs we need to handle: MCK1..4 */
 807         mov     tmp1, #1
 808 e_loop: cmp     tmp1, #5
 809         beq     e_done
 810
 811         /* Write MCK ID to retrieve the settings. */
 812         str     tmp1, [pmc, #AT91_PMC_MCR_V2]
 813         ldr     tmp2, [pmc, #AT91_PMC_MCR_V2]
 814
 815 e_save_mck1:
 816         cmp     tmp1, #1
 817         bne     e_save_mck2
 818         str     tmp2, .saved_mck1
 819         b       e_ps
 820
 821 e_save_mck2:
 822         cmp     tmp1, #2
 823         bne     e_save_mck3
 824         str     tmp2, .saved_mck2
 825         b       e_ps
 826
 827 e_save_mck3:
 828         cmp     tmp1, #3
 829         bne     e_save_mck4
 830         str     tmp2, .saved_mck3
 831         b       e_ps
 832
 833 e_save_mck4:
 834         str     tmp2, .saved_mck4
 835
 836 e_ps:
 837         /* Use CSS=MAINCK and DIV=1. */
 838         bic     tmp2, tmp2, #AT91_PMC_MCR_V2_CSS
 839         bic     tmp2, tmp2, #AT91_PMC_MCR_V2_DIV
 840         orr     tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
 841         orr     tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
 842         str     tmp2, [pmc, #AT91_PMC_MCR_V2]
 843
 844         wait_mckrdy tmp1
 845
 846         add     tmp1, tmp1, #1
 847         b       e_loop
 848
 849 e_done:
 850 #endif
 851 .endm
 852
 853 /**
 854  * at91_mckx_ps_restore: restore MCK1..4 settings
 855  *
 856  * Side effects: overwrites tmp1, tmp2
 857  */
 858 .macro at91_mckx_ps_restore
 859 #ifdef CONFIG_SOC_SAMA7
 860         ldr     pmc, .pmc_base
 861
 862         /* There are 4 MCKs we need to handle: MCK1..4 */
 863         mov     tmp1, #1
 864 r_loop: cmp     tmp1, #5
 865         beq     r_done
 866
 867 r_save_mck1:
 868         cmp     tmp1, #1
 869         bne     r_save_mck2
 870         ldr     tmp2, .saved_mck1
 871         b       r_ps
 872
 873 r_save_mck2:
 874         cmp     tmp1, #2
 875         bne     r_save_mck3
 876         ldr     tmp2, .saved_mck2
 877         b       r_ps
 878
 879 r_save_mck3:
 880         cmp     tmp1, #3
 881         bne     r_save_mck4
 882         ldr     tmp2, .saved_mck3
 883         b       r_ps
 884
 885 r_save_mck4:
 886         ldr     tmp2, .saved_mck4
 887
 888 r_ps:
 889         /* Write MCK ID to retrieve the settings. */
 890         str     tmp1, [pmc, #AT91_PMC_MCR_V2]
 891         ldr     tmp3, [pmc, #AT91_PMC_MCR_V2]
 892
 893         /* We need to restore CSS and DIV. */
 894         bic     tmp3, tmp3, #AT91_PMC_MCR_V2_CSS
 895         bic     tmp3, tmp3, #AT91_PMC_MCR_V2_DIV
 896         orr     tmp3, tmp3, tmp2
 897         bic     tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
 898         orr     tmp3, tmp3, tmp1
 899         orr     tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
 900         str     tmp2, [pmc, #AT91_PMC_MCR_V2]
 901
 902         wait_mckrdy tmp1
 903
 904         add     tmp1, tmp1, #1
 905         b       r_loop
 906 r_done:
 907 #endif
 908 .endm
 909
 910 .macro at91_ulp_mode
 911         at91_mckx_ps_enable
 912
 913         ldr     pmc, .pmc_base
 914         ldr     tmp2, .mckr_offset
 915         ldr     tmp3, .pm_mode
 916
 917         /* Save Master clock setting */
 918         ldr     tmp1, [pmc, tmp2]
 919         str     tmp1, .saved_mckr
 920
 921         /*
 922          * Set master clock source to:
 923          * - MAINCK if using ULP0 fast variant
 924          * - slow clock, otherwise
 925          */
 926         bic     tmp1, tmp1, #AT91_PMC_CSS
 927         cmp     tmp3, #AT91_PM_ULP0_FAST
 928         bne     save_mck
 929         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
 930 save_mck:
 931         str     tmp1, [pmc, tmp2]
 932
 933         mov     tmp3, #0
 934         wait_mckrdy tmp3
 935
 936         at91_plla_disable
 937
 938         /* Enable low power mode for 2.5V regulator. */
 939         at91_2_5V_reg_set_low_power 1
 940
 941         ldr     tmp3, .pm_mode
 942         cmp     tmp3, #AT91_PM_ULP1
 943         beq     ulp1_mode
 944
 945         at91_pm_ulp0_mode
 946         b       ulp_exit
 947
 948 ulp1_mode:
 949         at91_pm_ulp1_mode
 950         b       ulp_exit
 951
 952 ulp_exit:
 953         /* Disable low power mode for 2.5V regulator. */
 954         at91_2_5V_reg_set_low_power 0
 955
 956         ldr     pmc, .pmc_base
 957
 958         at91_plla_enable
 959
 960         /*
 961          * Restore master clock setting
 962          */
 963         ldr     tmp1, .mckr_offset
 964         ldr     tmp2, .saved_mckr
 965         str     tmp2, [pmc, tmp1]
 966
 967         mov     tmp3, #0
 968         wait_mckrdy tmp3
 969
 970         at91_mckx_ps_restore
 971 .endm
 972
 973 .macro at91_backup_mode
 974         /* Switch the master clock source to slow clock. */
 975         ldr     pmc, .pmc_base
 976         ldr     tmp2, .mckr_offset
 977         ldr     tmp1, [pmc, tmp2]
 978         bic     tmp1, tmp1, #AT91_PMC_CSS
 979         str     tmp1, [pmc, tmp2]
 980
 981         mov     tmp3, #0
 982         wait_mckrdy tmp3
 983
 984         /*BUMEN*/
 985         ldr     r0, .sfrbu
 986         mov     tmp1, #0x1
 987         str     tmp1, [r0, #0x10]
 988
 989         /* Wait for it. */
 990 1:      ldr     tmp1, [r0, #0x10]
 991         tst     tmp1, #0x1
 992         beq     1b
 993
 994         /* Shutdown */
 995         ldr     r0, .shdwc
 996         mov     tmp1, #0xA5000000
 997         add     tmp1, tmp1, #0x1
 998         at91_backup_set_lpm tmp1
 999         str     tmp1, [r0, #0]
1000 .endm
1001
1002 /*
1003  * void at91_suspend_sram_fn(struct at91_pm_data*)
1004  * @input param:
1005  *      @r0: base address of struct at91_pm_data
1006  */
1007 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
1008         .align 3
1009 ENTRY(at91_pm_suspend_in_sram)
1010         /* Save registers on stack */
1011         stmfd   sp!, {r4 - r12, lr}
1012
1013         /* Drain write buffer */
1014         mov     tmp1, #0
1015         mcr     p15, 0, tmp1, c7, c10, 4
1016
1017         ldr     tmp1, [r0, #PM_DATA_PMC]
1018         str     tmp1, .pmc_base
1019         ldr     tmp1, [r0, #PM_DATA_RAMC0]
1020         str     tmp1, .sramc_base
1021         ldr     tmp1, [r0, #PM_DATA_RAMC1]
1022         str     tmp1, .sramc1_base
1023         ldr     tmp1, [r0, #PM_DATA_RAMC_PHY]
1024         str     tmp1, .sramc_phy_base
1025         ldr     tmp1, [r0, #PM_DATA_MEMCTRL]
1026         str     tmp1, .memtype
1027         ldr     tmp1, [r0, #PM_DATA_MODE]
1028         str     tmp1, .pm_mode
1029         ldr     tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1030         str     tmp1, .mckr_offset
1031         ldr     tmp1, [r0, #PM_DATA_PMC_VERSION]
1032         str     tmp1, .pmc_version
1033         /* Both ldrne below are here to preload their address in the TLB */
1034         ldr     tmp1, [r0, #PM_DATA_SHDWC]
1035         str     tmp1, .shdwc
1036         cmp     tmp1, #0
1037         ldrne   tmp2, [tmp1, #0]
1038         ldr     tmp1, [r0, #PM_DATA_SFRBU]
1039         str     tmp1, .sfrbu
1040         cmp     tmp1, #0
1041         ldrne   tmp2, [tmp1, #0x10]
1042
1043         /* Active the self-refresh mode */
1044         at91_sramc_self_refresh_ena
1045
1046         ldr     r0, .pm_mode
1047         cmp     r0, #AT91_PM_STANDBY
1048         beq     standby
1049         cmp     r0, #AT91_PM_BACKUP
1050         beq     backup_mode
1051
1052         at91_ulp_mode
1053         b       exit_suspend
1054
1055 standby:
1056         /* Wait for interrupt */
1057         ldr     pmc, .pmc_base
1058         at91_cpu_idle
1059         b       exit_suspend
1060
1061 backup_mode:
1062         at91_backup_mode
1063
1064 exit_suspend:
1065         /* Exit the self-refresh mode */
1066         at91_sramc_self_refresh_dis
1067
1068         /* Restore registers, and return */
1069         ldmfd   sp!, {r4 - r12, pc}
1070 ENDPROC(at91_pm_suspend_in_sram)
1071
1072 .pmc_base:
1073         .word 0
1074 .sramc_base:
1075         .word 0
1076 .sramc1_base:
1077         .word 0
1078 .sramc_phy_base:
1079         .word 0
1080 .shdwc:
1081         .word 0
1082 .sfrbu:
1083         .word 0
1084 .memtype:
1085         .word 0
1086 .pm_mode:
1087         .word 0
1088 .mckr_offset:
1089         .word 0
1090 .pmc_version:
1091         .word 0
1092 .saved_mckr:
1093         .word 0
1094 .saved_pllar:
1095         .word 0
1096 .saved_sam9_lpr:
1097         .word 0
1098 .saved_sam9_lpr1:
1099         .word 0
1100 .saved_sam9_mdr:
1101         .word 0
1102 .saved_sam9_mdr1:
1103         .word 0
1104 .saved_osc_status:
1105         .word 0
1106 #ifdef CONFIG_SOC_SAMA7
1107 .saved_mck1:
1108         .word 0
1109 .saved_mck2:
1110         .word 0
1111 .saved_mck3:
1112         .word 0
1113 .saved_mck4:
1114         .word 0
1115 #endif
1116
1117 ENTRY(at91_pm_suspend_in_sram_sz)
1118         .word .-at91_pm_suspend_in_sram