1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
18 #include <linux/clk/at91_pmc.h>
19 #include <linux/platform_data/atmel.h>
21 #include <soc/at91/pm.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
37 * @canary: canary data for memory checking after exit from backup mode
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
44 unsigned long reserved;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
51 * struct at91_soc_pm - AT91 SoC power management data structure
52 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
53 * @config_pmc_ws: wakeup srouces configuration function for PMC
54 * @ws_ids: wakup sources of_device_id array
55 * @data: PM data to be used on last phase of suspend
56 * @bu: backup unit mapped data (for backup mode)
57 * @memcs: memory chip select
60 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
61 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
62 const struct of_device_id *ws_ids;
63 struct at91_pm_bu *bu;
64 struct at91_pm_data data;
69 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
70 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
71 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
78 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
80 static struct at91_soc_pm soc_pm = {
82 .standby_mode = AT91_PM_STANDBY,
83 .suspend_mode = AT91_PM_ULP0,
87 static const match_table_t pm_modes __initconst = {
88 { AT91_PM_STANDBY, "standby" },
89 { AT91_PM_ULP0, "ulp0" },
90 { AT91_PM_ULP0_FAST, "ulp0-fast" },
91 { AT91_PM_ULP1, "ulp1" },
92 { AT91_PM_BACKUP, "backup" },
96 #define at91_ramc_read(id, field) \
97 __raw_readl(soc_pm.data.ramc[id] + field)
99 #define at91_ramc_write(id, field, value) \
100 __raw_writel(value, soc_pm.data.ramc[id] + field)
102 static int at91_pm_valid_state(suspend_state_t state)
106 case PM_SUSPEND_STANDBY:
115 static int canary = 0xA5A5A5A5;
117 struct wakeup_source_info {
118 unsigned int pmc_fsmr_bit;
119 unsigned int shdwc_mr_bit;
123 static const struct wakeup_source_info ws_info[] = {
124 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
125 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
126 { .pmc_fsmr_bit = AT91_PMC_USBAL },
127 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
128 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
129 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
132 static const struct of_device_id sama5d2_ws_ids[] = {
133 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
134 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
135 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
136 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
137 { .compatible = "usb-ohci", .data = &ws_info[2] },
138 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
139 { .compatible = "usb-ehci", .data = &ws_info[2] },
140 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
144 static const struct of_device_id sam9x60_ws_ids[] = {
145 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
146 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
147 { .compatible = "usb-ohci", .data = &ws_info[2] },
148 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
149 { .compatible = "usb-ehci", .data = &ws_info[2] },
150 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
151 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
155 static const struct of_device_id sama7g5_ws_ids[] = {
156 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
157 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
158 { .compatible = "usb-ohci", .data = &ws_info[2] },
159 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
160 { .compatible = "usb-ehci", .data = &ws_info[2] },
161 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
162 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
166 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
168 const struct wakeup_source_info *wsi;
169 const struct of_device_id *match;
170 struct platform_device *pdev;
171 struct device_node *np;
172 unsigned int mode = 0, polarity = 0, val = 0;
174 if (pm_mode != AT91_PM_ULP1)
177 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
181 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
185 if (soc_pm.config_shdwc_ws)
186 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
189 val = readl(soc_pm.data.shdwc + 0x04);
191 /* Loop through defined wakeup sources. */
192 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
193 pdev = of_find_device_by_node(np);
197 if (device_may_wakeup(&pdev->dev)) {
200 /* Check if enabled on SHDWC. */
201 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
204 mode |= wsi->pmc_fsmr_bit;
205 if (wsi->set_polarity)
206 polarity |= wsi->pmc_fsmr_bit;
210 put_device(&pdev->dev);
214 if (soc_pm.config_pmc_ws)
215 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
217 pr_err("AT91: PM: no ULP1 wakeup sources found!");
220 return mode ? 0 : -EPERM;
223 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
229 val = readl(shdwc + 0x0c);
230 *mode |= (val & 0x3ff);
231 *polarity |= ((val >> 16) & 0x3ff);
236 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
238 writel(mode, pmc + AT91_PMC_FSMR);
239 writel(polarity, pmc + AT91_PMC_FSPR);
244 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
246 writel(mode, pmc + AT91_PMC_FSMR);
252 * Called after processes are frozen, but before we shutdown devices.
254 static int at91_pm_begin(suspend_state_t state)
260 soc_pm.data.mode = soc_pm.data.suspend_mode;
263 case PM_SUSPEND_STANDBY:
264 soc_pm.data.mode = soc_pm.data.standby_mode;
268 soc_pm.data.mode = -1;
271 ret = at91_pm_config_ws(soc_pm.data.mode, true);
275 if (soc_pm.data.mode == AT91_PM_BACKUP)
276 soc_pm.bu->suspended = 1;
278 soc_pm.bu->suspended = 0;
284 * Verify that all the clocks are correct before entering
287 static int at91_pm_verify_clocks(void)
292 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
294 /* USB must not be using PLLB */
295 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
296 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
300 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
301 for (i = 0; i < 4; i++) {
304 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
306 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
307 if (css != AT91_PMC_CSS_SLOW) {
308 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
317 * Call this from platform driver suspend() to see how deeply to suspend.
318 * For example, some controllers (like OHCI) need one of the PLL clocks
319 * in order to act as a wakeup source, and those are not available when
320 * going into slow clock mode.
322 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
323 * the very same problem (but not using at91 main_clk), and it'd be better
324 * to add one generic API rather than lots of platform-specific ones.
326 int at91_suspend_entering_slow_clock(void)
328 return (soc_pm.data.mode >= AT91_PM_ULP0);
330 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
332 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
333 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
334 extern u32 at91_pm_suspend_in_sram_sz;
336 static int at91_suspend_finish(unsigned long val)
340 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
342 * The 1st 8 words of memory might get corrupted in the process
343 * of DDR PHY recalibration; it is saved here in securam and it
344 * will be restored later, after recalibration, by bootloader
346 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
347 soc_pm.bu->ddr_phy_calibration[i] =
348 *((unsigned int *)soc_pm.memcs + (i - 1));
354 at91_suspend_sram_fn(&soc_pm.data);
359 static void at91_pm_suspend(suspend_state_t state)
361 if (soc_pm.data.mode == AT91_PM_BACKUP) {
362 cpu_suspend(0, at91_suspend_finish);
364 /* The SRAM is lost between suspend cycles */
365 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
366 &at91_pm_suspend_in_sram,
367 at91_pm_suspend_in_sram_sz);
369 at91_suspend_finish(0);
376 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
377 * event sources; and reduces DRAM power. But otherwise it's identical to
378 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
380 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
381 * suspend more deeply, the master clock switches to the clk32k and turns off
382 * the main oscillator
384 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
386 static int at91_pm_enter(suspend_state_t state)
388 #ifdef CONFIG_PINCTRL_AT91
390 * FIXME: this is needed to communicate between the pinctrl driver and
391 * the PM implementation in the machine. Possibly part of the PM
392 * implementation should be moved down into the pinctrl driver and get
393 * called as part of the generic suspend/resume path.
395 at91_pinctrl_gpio_suspend();
400 case PM_SUSPEND_STANDBY:
402 * Ensure that clocks are in a valid state.
404 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
405 !at91_pm_verify_clocks())
408 at91_pm_suspend(state);
417 pr_debug("AT91: PM - bogus suspend state %d\n", state);
422 #ifdef CONFIG_PINCTRL_AT91
423 at91_pinctrl_gpio_resume();
429 * Called right prior to thawing processes.
431 static void at91_pm_end(void)
433 at91_pm_config_ws(soc_pm.data.mode, false);
437 static const struct platform_suspend_ops at91_pm_ops = {
438 .valid = at91_pm_valid_state,
439 .begin = at91_pm_begin,
440 .enter = at91_pm_enter,
444 static struct platform_device at91_cpuidle_device = {
445 .name = "cpuidle-at91",
449 * The AT91RM9200 goes into self-refresh mode with this command, and will
450 * terminate self-refresh automatically on the next SDRAM access.
452 * Self-refresh mode is exited as soon as a memory access is made, but we don't
453 * know for sure when that happens. However, we need to restore the low-power
454 * mode if it was enabled before going idle. Restoring low-power mode while
455 * still in self-refresh is "not recommended", but seems to work.
457 static void at91rm9200_standby(void)
462 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
463 " str %2, [%1, %3]\n\t"
464 " mcr p15, 0, %0, c7, c0, 4\n\t"
466 : "r" (0), "r" (soc_pm.data.ramc[0]),
467 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
470 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
473 static void at91_ddr_standby(void)
475 /* Those two values allow us to delay self-refresh activation
478 u32 mdr, saved_mdr0, saved_mdr1 = 0;
479 u32 saved_lpr0, saved_lpr1 = 0;
481 /* LPDDR1 --> force DDR2 mode during self-refresh */
482 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
483 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
484 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
485 mdr |= AT91_DDRSDRC_MD_DDR2;
486 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
489 if (soc_pm.data.ramc[1]) {
490 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
491 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
492 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
493 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
494 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
495 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
496 mdr |= AT91_DDRSDRC_MD_DDR2;
497 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
501 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
502 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
503 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
505 /* self-refresh mode now */
506 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
507 if (soc_pm.data.ramc[1])
508 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
512 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
513 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
514 if (soc_pm.data.ramc[1]) {
515 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
516 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
520 static void sama5d3_ddr_standby(void)
525 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
526 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
527 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
529 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
533 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
536 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
539 static void at91sam9_sdram_standby(void)
542 u32 saved_lpr0, saved_lpr1 = 0;
544 if (soc_pm.data.ramc[1]) {
545 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
546 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
547 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
550 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
551 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
552 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
554 /* self-refresh mode now */
555 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
556 if (soc_pm.data.ramc[1])
557 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
561 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
562 if (soc_pm.data.ramc[1])
563 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
568 unsigned int memctrl;
571 static const struct ramc_info ramc_infos[] __initconst = {
572 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
573 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
574 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
575 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
578 static const struct of_device_id ramc_ids[] __initconst = {
579 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
580 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
581 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
582 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
583 { .compatible = "microchip,sama7g5-uddrc", },
587 static const struct of_device_id ramc_phy_ids[] __initconst = {
588 { .compatible = "microchip,sama7g5-ddr3phy", },
592 static __init void at91_dt_ramc(bool phy_mandatory)
594 struct device_node *np;
595 const struct of_device_id *of_id;
597 void *standby = NULL;
598 const struct ramc_info *ramc;
600 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
601 soc_pm.data.ramc[idx] = of_iomap(np, 0);
602 if (!soc_pm.data.ramc[idx])
603 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
608 standby = ramc->idle;
609 soc_pm.data.memctrl = ramc->memctrl;
616 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
618 /* Lookup for DDR PHY node, if any. */
619 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
620 soc_pm.data.ramc_phy = of_iomap(np, 0);
621 if (!soc_pm.data.ramc_phy)
622 panic(pr_fmt("unable to map ramc phy cpu registers\n"));
625 if (phy_mandatory && !soc_pm.data.ramc_phy)
626 panic(pr_fmt("DDR PHY is mandatory!\n"));
629 pr_warn("ramc no standby function available\n");
633 at91_cpuidle_device.dev.platform_data = standby;
636 static void at91rm9200_idle(void)
639 * Disable the processor clock. The processor will be automatically
640 * re-enabled by an interrupt or by a reset.
642 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
645 static void at91sam9_idle(void)
647 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
651 static void __init at91_pm_sram_init(void)
653 struct gen_pool *sram_pool;
654 phys_addr_t sram_pbase;
655 unsigned long sram_base;
656 struct device_node *node;
657 struct platform_device *pdev = NULL;
659 for_each_compatible_node(node, NULL, "mmio-sram") {
660 pdev = of_find_device_by_node(node);
668 pr_warn("%s: failed to find sram device!\n", __func__);
672 sram_pool = gen_pool_get(&pdev->dev, NULL);
674 pr_warn("%s: sram pool unavailable!\n", __func__);
678 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
680 pr_warn("%s: unable to alloc sram!\n", __func__);
684 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
685 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
686 at91_pm_suspend_in_sram_sz, false);
687 if (!at91_suspend_sram_fn) {
688 pr_warn("SRAM: Could not map\n");
692 /* Copy the pm suspend handler to SRAM */
693 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
694 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
698 put_device(&pdev->dev);
702 static bool __init at91_is_pm_mode_active(int pm_mode)
704 return (soc_pm.data.standby_mode == pm_mode ||
705 soc_pm.data.suspend_mode == pm_mode);
708 static int __init at91_pm_backup_scan_memcs(unsigned long node,
709 const char *uname, int depth,
717 /* Memory node already located. */
721 type = of_get_flat_dt_prop(node, "device_type", NULL);
723 /* We are scanning "memory" nodes only. */
724 if (!type || strcmp(type, "memory"))
727 reg = of_get_flat_dt_prop(node, "reg", &size);
729 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
736 static int __init at91_pm_backup_init(void)
738 struct gen_pool *sram_pool;
739 struct device_node *np;
740 struct platform_device *pdev;
741 int ret = -ENODEV, located = 0;
743 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
744 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
747 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
750 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
754 pdev = of_find_device_by_node(np);
757 pr_warn("%s: failed to find securam device!\n", __func__);
761 sram_pool = gen_pool_get(&pdev->dev, NULL);
763 pr_warn("%s: securam pool unavailable!\n", __func__);
767 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
769 pr_warn("%s: unable to alloc securam!\n", __func__);
774 soc_pm.bu->suspended = 0;
775 soc_pm.bu->canary = __pa_symbol(&canary);
776 soc_pm.bu->resume = __pa_symbol(cpu_resume);
777 if (soc_pm.data.ramc_phy) {
778 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
783 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
790 put_device(&pdev->dev);
794 static const struct of_device_id atmel_shdwc_ids[] = {
795 { .compatible = "atmel,sama5d2-shdwc" },
796 { .compatible = "microchip,sam9x60-shdwc" },
797 { .compatible = "microchip,sama7g5-shdwc" },
801 static void __init at91_pm_modes_init(const u32 *maps, int len)
803 struct device_node *np;
806 ret = at91_pm_backup_init();
808 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
809 soc_pm.data.standby_mode = AT91_PM_ULP0;
810 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
811 soc_pm.data.suspend_mode = AT91_PM_ULP0;
814 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
815 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
816 np = of_find_matching_node(NULL, atmel_shdwc_ids);
818 pr_warn("%s: failed to find shdwc!\n", __func__);
820 /* Use ULP0 if it doesn't needs SHDWC.*/
821 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
824 mode = AT91_PM_STANDBY;
826 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
827 soc_pm.data.standby_mode = mode;
828 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
829 soc_pm.data.suspend_mode = mode;
831 soc_pm.data.shdwc = of_iomap(np, 0);
836 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
837 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
838 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
840 pr_warn("%s: failed to find sfrbu!\n", __func__);
843 * Use ULP0 if it doesn't need SHDWC or if SHDWC
844 * was already located.
846 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
850 mode = AT91_PM_STANDBY;
852 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
853 soc_pm.data.standby_mode = mode;
854 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
855 soc_pm.data.suspend_mode = mode;
857 soc_pm.data.sfrbu = of_iomap(np, 0);
862 /* Unmap all unnecessary. */
863 if (soc_pm.data.shdwc &&
864 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
865 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
866 iounmap(soc_pm.data.shdwc);
867 soc_pm.data.shdwc = NULL;
870 if (soc_pm.data.sfrbu &&
871 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
872 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
873 iounmap(soc_pm.data.sfrbu);
874 soc_pm.data.sfrbu = NULL;
881 unsigned long uhp_udp_mask;
883 unsigned long version;
886 static const struct pmc_info pmc_infos[] __initconst = {
888 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
890 .version = AT91_PMC_V1,
894 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
896 .version = AT91_PMC_V1,
899 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
901 .version = AT91_PMC_V1,
905 .version = AT91_PMC_V1,
908 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
910 .version = AT91_PMC_V2,
914 .version = AT91_PMC_V2,
919 static const struct of_device_id atmel_pmc_ids[] __initconst = {
920 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
921 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
922 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
923 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
924 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
925 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
926 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
927 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
928 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
929 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
930 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
931 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
932 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
936 static void __init at91_pm_modes_validate(const int *modes, int len)
938 u8 i, standby = 0, suspend = 0;
941 for (i = 0; i < len; i++) {
942 if (standby && suspend)
945 if (modes[i] == soc_pm.data.standby_mode && !standby) {
950 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
957 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
960 mode = AT91_PM_STANDBY;
962 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
963 pm_modes[soc_pm.data.standby_mode].pattern,
964 pm_modes[mode].pattern);
965 soc_pm.data.standby_mode = mode;
969 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
970 mode = AT91_PM_STANDBY;
974 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
975 pm_modes[soc_pm.data.suspend_mode].pattern,
976 pm_modes[mode].pattern);
977 soc_pm.data.suspend_mode = mode;
981 static void __init at91_pm_init(void (*pm_idle)(void))
983 struct device_node *pmc_np;
984 const struct of_device_id *of_id;
985 const struct pmc_info *pmc;
987 if (at91_cpuidle_device.dev.platform_data)
988 platform_device_register(&at91_cpuidle_device);
990 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
991 soc_pm.data.pmc = of_iomap(pmc_np, 0);
993 if (!soc_pm.data.pmc) {
994 pr_err("AT91: PM not supported, PMC not found\n");
999 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1000 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1001 soc_pm.data.pmc_version = pmc->version;
1004 arm_pm_idle = pm_idle;
1006 at91_pm_sram_init();
1008 if (at91_suspend_sram_fn) {
1009 suspend_set_ops(&at91_pm_ops);
1010 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1011 pm_modes[soc_pm.data.standby_mode].pattern,
1012 pm_modes[soc_pm.data.suspend_mode].pattern);
1014 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1018 void __init at91rm9200_pm_init(void)
1020 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1024 * Force STANDBY and ULP0 mode to avoid calling
1025 * at91_pm_modes_validate() which may increase booting time.
1026 * Platform supports anyway only STANDBY and ULP0 modes.
1028 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1029 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1031 at91_dt_ramc(false);
1034 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1036 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1038 at91_pm_init(at91rm9200_idle);
1041 void __init sam9x60_pm_init(void)
1043 static const int modes[] __initconst = {
1044 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1046 static const int iomaps[] __initconst = {
1047 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1050 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1053 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1054 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1055 at91_dt_ramc(false);
1058 soc_pm.ws_ids = sam9x60_ws_ids;
1059 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1062 void __init at91sam9_pm_init(void)
1064 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1068 * Force STANDBY and ULP0 mode to avoid calling
1069 * at91_pm_modes_validate() which may increase booting time.
1070 * Platform supports anyway only STANDBY and ULP0 modes.
1072 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1073 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1075 at91_dt_ramc(false);
1076 at91_pm_init(at91sam9_idle);
1079 void __init sama5_pm_init(void)
1081 static const int modes[] __initconst = {
1082 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1085 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1088 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1089 at91_dt_ramc(false);
1093 void __init sama5d2_pm_init(void)
1095 static const int modes[] __initconst = {
1096 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1099 static const u32 iomaps[] __initconst = {
1100 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1101 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1102 AT91_PM_IOMAP(SFRBU),
1105 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1108 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1109 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1110 at91_dt_ramc(false);
1113 soc_pm.ws_ids = sama5d2_ws_ids;
1114 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1115 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1118 void __init sama7_pm_init(void)
1120 static const int modes[] __initconst = {
1121 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1123 static const u32 iomaps[] __initconst = {
1124 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1125 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1126 AT91_PM_IOMAP(SHDWC),
1127 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1128 AT91_PM_IOMAP(SHDWC),
1131 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1134 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1137 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1140 soc_pm.ws_ids = sama7g5_ws_ids;
1141 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1144 static int __init at91_pm_modes_select(char *str)
1147 substring_t args[MAX_OPT_ARGS];
1148 int standby, suspend;
1153 s = strsep(&str, ",");
1154 standby = match_token(s, pm_modes, args);
1158 suspend = match_token(str, pm_modes, args);
1162 soc_pm.data.standby_mode = standby;
1163 soc_pm.data.suspend_mode = suspend;
1167 early_param("atmel.pm_modes", at91_pm_modes_select);