arch/arm/mach-at91/include/mach/sama5_sfr.h

   1 /*
   2  * Special Function Register (SFR)
   3  *
   4  * Copyright (C) 2014 Atmel
   5  *                    Bo Shen <voice.shen@atmel.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __SAMA5_SFR_H
  11 #define __SAMA5_SFR_H
  12
  13 struct atmel_sfr {
  14         u32 reserved1;  /* 0x00 */
  15         u32 ddrcfg;     /* 0x04: DDR Configuration Register */
  16         u32 reserved2;  /* 0x08 */
  17         u32 reserved3;  /* 0x0c */
  18         u32 ohciicr;    /* 0x10: OHCI Interrupt Configuration Register */
  19         u32 ohciisr;    /* 0x14: OHCI Interrupt Status Register */
  20         u32 reserved4[4];       /* 0x18 ~ 0x24 */
  21         u32 secure;             /* 0x28: Security Configuration Register */
  22         u32 reserved5[5];       /* 0x2c ~ 0x3c */
  23         u32 ebicfg;             /* 0x40: EBI Configuration Register */
  24         u32 reserved6[2];       /* 0x44 ~ 0x48 */
  25         u32 sn0;                /* 0x4c */
  26         u32 sn1;                /* 0x50 */
  27         u32 aicredir;   /* 0x54 */
  28 };
  29
  30 /* Bit field in DDRCFG */
  31 #define ATMEL_SFR_DDRCFG_FDQIEN         0x00010000
  32 #define ATMEL_SFR_DDRCFG_FDQSIEN        0x00020000
  33
  34 /* Bit field in AICREDIR */
  35 #define ATMEL_SFR_AICREDIR_NSAIC        0x00000001
  36
  37 #endif