2 * linux/arch/arm/mach-at91/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
27 #include <mach/hardware.h>
28 #include <mach/at91_pmc.h>
36 * There's a lot more which can be done with clocks, including cpufreq
37 * integration, slow clock mode support (for system suspend), letting
38 * PLLB be used at other rates (on boards that don't need USB), etc.
41 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
44 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
48 * Chips have some kind of clocks : group them by functionality
50 #define cpu_has_utmi() ( cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9g45())
53 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
54 || cpu_is_at91sam9g45())
56 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
58 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
59 || cpu_is_at91sam9g45()))
61 #define cpu_has_upll() (cpu_is_at91sam9g45())
63 /* USB host HS & FS */
64 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
66 /* USB device FS only */
67 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
68 || cpu_is_at91sam9g45()))
70 static LIST_HEAD(clocks);
71 static DEFINE_SPINLOCK(clk_lock);
73 static u32 at91_pllb_usb_init;
76 * Four primary clock sources: two crystal oscillators (32K, main), and
77 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
78 * 48 MHz (unless no USB function clocks are needed). The main clock and
79 * both PLLs are turned off to run in "slow clock mode" (system suspend).
81 static struct clk clk32k = {
83 .rate_hz = AT91_SLOW_CLOCK,
84 .users = 1, /* always on */
86 .type = CLK_TYPE_PRIMARY,
88 static struct clk main_clk = {
90 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
92 .type = CLK_TYPE_PRIMARY,
94 static struct clk plla = {
97 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
99 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
102 static void pllb_mode(struct clk *clk, int is_on)
107 is_on = AT91_PMC_LOCKB;
108 value = at91_pllb_usb_init;
112 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
113 at91_sys_write(AT91_CKGR_PLLBR, value);
117 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
120 static struct clk pllb = {
123 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
126 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
129 static void pmc_sys_mode(struct clk *clk, int is_on)
132 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
134 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
137 static void pmc_uckr_mode(struct clk *clk, int is_on)
139 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
141 if (cpu_is_at91sam9g45()) {
143 uckr |= AT91_PMC_BIASEN;
145 uckr &= ~AT91_PMC_BIASEN;
149 is_on = AT91_PMC_LOCKU;
150 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
152 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
156 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
159 /* USB function clocks (PLLB must be 48 MHz) */
160 static struct clk udpck = {
163 .mode = pmc_sys_mode,
165 struct clk utmi_clk = {
168 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
169 .mode = pmc_uckr_mode,
170 .type = CLK_TYPE_PLL,
172 static struct clk uhpck = {
174 /*.parent = ... we choose parent at runtime */
175 .mode = pmc_sys_mode,
180 * The master clock is divided from the CPU clock (by 1-4). It's used for
181 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
182 * (e.g baud rate generation). It's sourced from one of the primary clocks.
186 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
189 static void pmc_periph_mode(struct clk *clk, int is_on)
192 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
194 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
197 static struct clk __init *at91_css_to_clk(unsigned long css)
200 case AT91_PMC_CSS_SLOW:
202 case AT91_PMC_CSS_MAIN:
204 case AT91_PMC_CSS_PLLA:
206 case AT91_PMC_CSS_PLLB:
208 /* CSS_PLLB == CSS_UPLL */
210 else if (cpu_has_pllb())
217 static void __clk_enable(struct clk *clk)
220 __clk_enable(clk->parent);
221 if (clk->users++ == 0 && clk->mode)
225 int clk_enable(struct clk *clk)
229 spin_lock_irqsave(&clk_lock, flags);
231 spin_unlock_irqrestore(&clk_lock, flags);
234 EXPORT_SYMBOL(clk_enable);
236 static void __clk_disable(struct clk *clk)
238 BUG_ON(clk->users == 0);
239 if (--clk->users == 0 && clk->mode)
242 __clk_disable(clk->parent);
245 void clk_disable(struct clk *clk)
249 spin_lock_irqsave(&clk_lock, flags);
251 spin_unlock_irqrestore(&clk_lock, flags);
253 EXPORT_SYMBOL(clk_disable);
255 unsigned long clk_get_rate(struct clk *clk)
260 spin_lock_irqsave(&clk_lock, flags);
263 if (rate || !clk->parent)
267 spin_unlock_irqrestore(&clk_lock, flags);
270 EXPORT_SYMBOL(clk_get_rate);
272 /*------------------------------------------------------------------------*/
274 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
277 * For now, only the programmable clocks support reparenting (MCK could
278 * do this too, with care) or rate changing (the PLLs could do this too,
279 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
280 * a better rate match; we don't.
283 long clk_round_rate(struct clk *clk, unsigned long rate)
287 unsigned long actual;
288 unsigned long prev = ULONG_MAX;
290 if (!clk_is_programmable(clk))
292 spin_lock_irqsave(&clk_lock, flags);
294 actual = clk->parent->rate_hz;
295 for (prescale = 0; prescale < 7; prescale++) {
299 if (actual && actual <= rate) {
300 if ((prev - rate) < (rate - actual)) {
309 spin_unlock_irqrestore(&clk_lock, flags);
310 return (prescale < 7) ? actual : -ENOENT;
312 EXPORT_SYMBOL(clk_round_rate);
314 int clk_set_rate(struct clk *clk, unsigned long rate)
318 unsigned long actual;
320 if (!clk_is_programmable(clk))
324 spin_lock_irqsave(&clk_lock, flags);
326 actual = clk->parent->rate_hz;
327 for (prescale = 0; prescale < 7; prescale++) {
328 if (actual && actual <= rate) {
331 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
332 pckr &= AT91_PMC_CSS; /* clock selection */
333 pckr |= prescale << 2;
334 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
335 clk->rate_hz = actual;
341 spin_unlock_irqrestore(&clk_lock, flags);
342 return (prescale < 7) ? actual : -ENOENT;
344 EXPORT_SYMBOL(clk_set_rate);
346 struct clk *clk_get_parent(struct clk *clk)
350 EXPORT_SYMBOL(clk_get_parent);
352 int clk_set_parent(struct clk *clk, struct clk *parent)
358 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
361 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
364 spin_lock_irqsave(&clk_lock, flags);
366 clk->rate_hz = parent->rate_hz;
367 clk->parent = parent;
368 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
370 spin_unlock_irqrestore(&clk_lock, flags);
373 EXPORT_SYMBOL(clk_set_parent);
375 /* establish PCK0..PCKN parentage and rate */
376 static void __init init_programmable_clock(struct clk *clk)
381 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
382 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
383 clk->parent = parent;
384 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
387 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
389 /*------------------------------------------------------------------------*/
391 #ifdef CONFIG_DEBUG_FS
393 static int at91_clk_show(struct seq_file *s, void *unused)
395 u32 scsr, pcsr, uckr = 0, sr;
398 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
399 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
400 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
401 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
402 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
404 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
406 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
407 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
409 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
410 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
414 list_for_each_entry(clk, &clocks, node) {
417 if (clk->mode == pmc_sys_mode)
418 state = (scsr & clk->pmc_mask) ? "on" : "off";
419 else if (clk->mode == pmc_periph_mode)
420 state = (pcsr & clk->pmc_mask) ? "on" : "off";
421 else if (clk->mode == pmc_uckr_mode)
422 state = (uckr & clk->pmc_mask) ? "on" : "off";
423 else if (clk->pmc_mask)
424 state = (sr & clk->pmc_mask) ? "on" : "off";
425 else if (clk == &clk32k || clk == &main_clk)
430 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
431 clk->name, clk->users, state, clk_get_rate(clk),
432 clk->parent ? clk->parent->name : "");
437 static int at91_clk_open(struct inode *inode, struct file *file)
439 return single_open(file, at91_clk_show, NULL);
442 static const struct file_operations at91_clk_operations = {
443 .open = at91_clk_open,
446 .release = single_release,
449 static int __init at91_clk_debugfs_init(void)
451 /* /sys/kernel/debug/at91_clk */
452 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
456 postcore_initcall(at91_clk_debugfs_init);
460 /*------------------------------------------------------------------------*/
462 /* Register a new clock */
463 static void __init at91_clk_add(struct clk *clk)
465 list_add_tail(&clk->node, &clocks);
467 clk->cl.con_id = clk->name;
469 clkdev_add(&clk->cl);
472 int __init clk_register(struct clk *clk)
474 if (clk_is_peripheral(clk)) {
477 clk->mode = pmc_periph_mode;
479 else if (clk_is_sys(clk)) {
481 clk->mode = pmc_sys_mode;
483 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
484 else if (clk_is_programmable(clk)) {
485 clk->mode = pmc_sys_mode;
486 init_programmable_clock(clk);
495 /*------------------------------------------------------------------------*/
497 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
502 mul = (reg >> 16) & 0x7ff;
512 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
514 if (pll == &pllb && (reg & AT91_PMC_USB96M))
520 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
522 unsigned i, div = 0, mul = 0, diff = 1 << 30;
523 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
525 /* PLL output max 240 MHz (or 180 MHz per errata) */
526 if (out_freq > 240000000)
529 for (i = 1; i < 256; i++) {
531 unsigned input, mul1;
534 * PLL input between 1MHz and 32MHz per spec, but lower
535 * frequences seem necessary in some cases so allow 100K.
536 * Warning: some newer products need 2MHz min.
538 input = main_freq / i;
539 if (cpu_is_at91sam9g20() && input < 2000000)
543 if (input > 32000000)
546 mul1 = out_freq / input;
547 if (cpu_is_at91sam9g20() && mul > 63)
554 diff1 = out_freq - input * mul1;
565 if (i == 256 && diff > (out_freq >> 5))
567 return ret | ((mul - 1) << 16) | div;
572 static struct clk *const standard_pmc_clocks[] __initdata = {
573 /* four primary clocks */
582 /* PLLB generated USB full speed clock init */
583 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
586 * USB clock init: choose 48 MHz PLLB value,
587 * disable 48MHz clock during usb peripheral suspend.
589 * REVISIT: assumes MCK doesn't derive from PLLB!
591 uhpck.parent = &pllb;
593 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
594 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
595 if (cpu_is_at91rm9200()) {
596 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
597 udpck.pmc_mask = AT91RM9200_PMC_UDP;
598 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
599 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
600 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
601 cpu_is_at91sam9g10()) {
602 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
603 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
605 at91_sys_write(AT91_CKGR_PLLBR, 0);
607 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
608 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
611 /* UPLL generated USB full speed clock init */
612 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
615 * USB clock init: choose 480 MHz from UPLL,
617 unsigned int usbr = AT91_PMC_USBS_UPLL;
619 /* Setup divider by 10 to reach 48 MHz */
620 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
622 at91_sys_write(AT91_PMC_USB, usbr);
624 /* Now set uhpck values */
625 uhpck.parent = &utmi_clk;
626 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
627 uhpck.rate_hz = utmi_clk.rate_hz;
628 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
631 int __init at91_clock_init(unsigned long main_clock)
633 unsigned tmp, freq, mckr;
635 int pll_overclock = false;
638 * When the bootloader initialized the main oscillator correctly,
639 * there's no problem using the cycle counter. But if it didn't,
640 * or when using oscillator bypass mode, we must be told the speed
645 tmp = at91_sys_read(AT91_CKGR_MCFR);
646 } while (!(tmp & AT91_PMC_MAINRDY));
647 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
649 main_clk.rate_hz = main_clock;
651 /* report if PLLA is more than mildly overclocked */
652 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
653 if (cpu_has_300M_plla()) {
654 if (plla.rate_hz > 300000000)
655 pll_overclock = true;
656 } else if (cpu_has_800M_plla()) {
657 if (plla.rate_hz > 800000000)
658 pll_overclock = true;
660 if (plla.rate_hz > 209000000)
661 pll_overclock = true;
664 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
666 if (cpu_is_at91sam9g45()) {
667 mckr = at91_sys_read(AT91_PMC_MCKR);
668 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
671 if (!cpu_has_pllb() && cpu_has_upll()) {
672 /* setup UTMI clock as the fourth primary clock
673 * (instead of pllb) */
674 utmi_clk.type |= CLK_TYPE_PRIMARY;
682 if (cpu_has_utmi()) {
684 * multiplier is hard-wired to 40
685 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
687 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
694 at91_pllb_usbfs_clock_init(main_clock);
696 /* assumes that we choose UPLL for USB and not PLLA */
697 at91_upll_usbfs_clock_init(main_clock);
700 * MCK and CPU derive from one of those primary clocks.
701 * For now, assume this parentage won't change.
703 mckr = at91_sys_read(AT91_PMC_MCKR);
704 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
705 freq = mck.parent->rate_hz;
706 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
707 if (cpu_is_at91rm9200()) {
708 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
709 } else if (cpu_is_at91sam9g20()) {
710 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
711 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
712 if (mckr & AT91_PMC_PDIV)
713 freq /= 2; /* processor clock division */
714 } else if (cpu_is_at91sam9g45()) {
715 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
716 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
718 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
721 /* Register the PMC's standard clocks */
722 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
723 at91_clk_add(standard_pmc_clocks[i]);
729 at91_clk_add(&uhpck);
732 at91_clk_add(&udpck);
735 at91_clk_add(&utmi_clk);
737 /* MCK and CPU clock are "always on" */
740 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
741 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
742 (unsigned) main_clock / 1000000,
743 ((unsigned) main_clock % 1000000) / 1000);
749 * Several unused clocks may be active. Turn them off.
751 static int __init at91_clock_reset(void)
753 unsigned long pcdr = 0;
754 unsigned long scdr = 0;
757 list_for_each_entry(clk, &clocks, node) {
761 if (clk->mode == pmc_periph_mode)
762 pcdr |= clk->pmc_mask;
764 if (clk->mode == pmc_sys_mode)
765 scdr |= clk->pmc_mask;
767 pr_debug("Clocks: disable unused %s\n", clk->name);
770 at91_sys_write(AT91_PMC_PCDR, pcdr);
771 at91_sys_write(AT91_PMC_SCDR, scdr);
775 late_initcall(at91_clock_reset);