2 * On-Chip devices setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18 #include <linux/atmel-mci.h>
21 #include <video/atmel_lcdc.h>
23 #include <mach/board.h>
24 #include <mach/gpio.h>
25 #include <mach/at91sam9g45.h>
26 #include <mach/at91sam9g45_matrix.h>
27 #include <mach/at91sam9_smc.h>
28 #include <mach/at_hdmac.h>
29 #include <mach/atmel-mci.h>
34 /* --------------------------------------------------------------------
35 * HDMAC - AHB DMA Controller
36 * -------------------------------------------------------------------- */
38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
41 static struct at_dma_platform_data atdma_pdata = {
45 static struct resource hdmac_resources[] = {
47 .start = AT91_BASE_SYS + AT91_DMA,
48 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
49 .flags = IORESOURCE_MEM,
52 .start = AT91SAM9G45_ID_DMA,
53 .end = AT91SAM9G45_ID_DMA,
54 .flags = IORESOURCE_IRQ,
58 static struct platform_device at_hdmac_device = {
62 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
66 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources),
70 void __init at91_add_device_hdmac(void)
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
74 platform_device_register(&at_hdmac_device);
77 void __init at91_add_device_hdmac(void) {}
81 /* --------------------------------------------------------------------
83 * -------------------------------------------------------------------- */
85 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
86 static u64 ohci_dmamask = DMA_BIT_MASK(32);
87 static struct at91_usbh_data usbh_ohci_data;
89 static struct resource usbh_ohci_resources[] = {
91 .start = AT91SAM9G45_OHCI_BASE,
92 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
93 .flags = IORESOURCE_MEM,
96 .start = AT91SAM9G45_ID_UHPHS,
97 .end = AT91SAM9G45_ID_UHPHS,
98 .flags = IORESOURCE_IRQ,
102 static struct platform_device at91_usbh_ohci_device = {
106 .dma_mask = &ohci_dmamask,
107 .coherent_dma_mask = DMA_BIT_MASK(32),
108 .platform_data = &usbh_ohci_data,
110 .resource = usbh_ohci_resources,
111 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
114 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
121 /* Enable VBus control for UHP ports */
122 for (i = 0; i < data->ports; i++) {
123 if (data->vbus_pin[i])
124 at91_set_gpio_output(data->vbus_pin[i], 0);
127 usbh_ohci_data = *data;
128 platform_device_register(&at91_usbh_ohci_device);
131 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
135 /* --------------------------------------------------------------------
137 * Needs an OHCI host for low and full speed management
138 * -------------------------------------------------------------------- */
140 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
141 static u64 ehci_dmamask = DMA_BIT_MASK(32);
142 static struct at91_usbh_data usbh_ehci_data;
144 static struct resource usbh_ehci_resources[] = {
146 .start = AT91SAM9G45_EHCI_BASE,
147 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
148 .flags = IORESOURCE_MEM,
151 .start = AT91SAM9G45_ID_UHPHS,
152 .end = AT91SAM9G45_ID_UHPHS,
153 .flags = IORESOURCE_IRQ,
157 static struct platform_device at91_usbh_ehci_device = {
158 .name = "atmel-ehci",
161 .dma_mask = &ehci_dmamask,
162 .coherent_dma_mask = DMA_BIT_MASK(32),
163 .platform_data = &usbh_ehci_data,
165 .resource = usbh_ehci_resources,
166 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
169 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
176 /* Enable VBus control for UHP ports */
177 for (i = 0; i < data->ports; i++) {
178 if (data->vbus_pin[i])
179 at91_set_gpio_output(data->vbus_pin[i], 0);
182 usbh_ehci_data = *data;
183 platform_device_register(&at91_usbh_ehci_device);
186 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
190 /* --------------------------------------------------------------------
191 * USB HS Device (Gadget)
192 * -------------------------------------------------------------------- */
194 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
195 static struct resource usba_udc_resources[] = {
197 .start = AT91SAM9G45_UDPHS_FIFO,
198 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
199 .flags = IORESOURCE_MEM,
202 .start = AT91SAM9G45_BASE_UDPHS,
203 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
204 .flags = IORESOURCE_MEM,
207 .start = AT91SAM9G45_ID_UDPHS,
208 .end = AT91SAM9G45_ID_UDPHS,
209 .flags = IORESOURCE_IRQ,
213 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
217 .fifo_size = maxpkt, \
223 static struct usba_ep_data usba_udc_ep[] __initdata = {
224 EP("ep0", 0, 64, 1, 0, 0),
225 EP("ep1", 1, 1024, 2, 1, 1),
226 EP("ep2", 2, 1024, 2, 1, 1),
227 EP("ep3", 3, 1024, 3, 1, 0),
228 EP("ep4", 4, 1024, 3, 1, 0),
229 EP("ep5", 5, 1024, 3, 1, 1),
230 EP("ep6", 6, 1024, 3, 1, 1),
236 * pdata doesn't have room for any endpoints, so we need to
237 * append room for the ones we need right after it.
240 struct usba_platform_data pdata;
241 struct usba_ep_data ep[7];
244 static struct platform_device at91_usba_udc_device = {
245 .name = "atmel_usba_udc",
248 .platform_data = &usba_udc_data.pdata,
250 .resource = usba_udc_resources,
251 .num_resources = ARRAY_SIZE(usba_udc_resources),
254 void __init at91_add_device_usba(struct usba_platform_data *data)
256 usba_udc_data.pdata.vbus_pin = -EINVAL;
257 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
258 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
260 if (data && data->vbus_pin > 0) {
261 at91_set_gpio_input(data->vbus_pin, 0);
262 at91_set_deglitch(data->vbus_pin, 1);
263 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
266 /* Pullup pin is handled internally by USB device peripheral */
268 platform_device_register(&at91_usba_udc_device);
271 void __init at91_add_device_usba(struct usba_platform_data *data) {}
275 /* --------------------------------------------------------------------
277 * -------------------------------------------------------------------- */
279 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
280 static u64 eth_dmamask = DMA_BIT_MASK(32);
281 static struct at91_eth_data eth_data;
283 static struct resource eth_resources[] = {
285 .start = AT91SAM9G45_BASE_EMAC,
286 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
287 .flags = IORESOURCE_MEM,
290 .start = AT91SAM9G45_ID_EMAC,
291 .end = AT91SAM9G45_ID_EMAC,
292 .flags = IORESOURCE_IRQ,
296 static struct platform_device at91sam9g45_eth_device = {
300 .dma_mask = ð_dmamask,
301 .coherent_dma_mask = DMA_BIT_MASK(32),
302 .platform_data = ð_data,
304 .resource = eth_resources,
305 .num_resources = ARRAY_SIZE(eth_resources),
308 void __init at91_add_device_eth(struct at91_eth_data *data)
313 if (data->phy_irq_pin) {
314 at91_set_gpio_input(data->phy_irq_pin, 0);
315 at91_set_deglitch(data->phy_irq_pin, 1);
318 /* Pins used for MII and RMII */
319 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
320 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
321 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
322 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
323 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
324 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
325 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
326 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
327 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
328 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
330 if (!data->is_rmii) {
331 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
332 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
333 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
334 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
335 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
336 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
337 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
338 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
342 platform_device_register(&at91sam9g45_eth_device);
345 void __init at91_add_device_eth(struct at91_eth_data *data) {}
349 /* --------------------------------------------------------------------
351 * -------------------------------------------------------------------- */
353 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
354 static u64 mmc_dmamask = DMA_BIT_MASK(32);
355 static struct mci_platform_data mmc0_data, mmc1_data;
357 static struct resource mmc0_resources[] = {
359 .start = AT91SAM9G45_BASE_MCI0,
360 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
361 .flags = IORESOURCE_MEM,
364 .start = AT91SAM9G45_ID_MCI0,
365 .end = AT91SAM9G45_ID_MCI0,
366 .flags = IORESOURCE_IRQ,
370 static struct platform_device at91sam9g45_mmc0_device = {
374 .dma_mask = &mmc_dmamask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
376 .platform_data = &mmc0_data,
378 .resource = mmc0_resources,
379 .num_resources = ARRAY_SIZE(mmc0_resources),
382 static struct resource mmc1_resources[] = {
384 .start = AT91SAM9G45_BASE_MCI1,
385 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
389 .start = AT91SAM9G45_ID_MCI1,
390 .end = AT91SAM9G45_ID_MCI1,
391 .flags = IORESOURCE_IRQ,
395 static struct platform_device at91sam9g45_mmc1_device = {
399 .dma_mask = &mmc_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 .platform_data = &mmc1_data,
403 .resource = mmc1_resources,
404 .num_resources = ARRAY_SIZE(mmc1_resources),
407 /* Consider only one slot : slot 0 */
408 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
414 /* Must have at least one usable slot */
415 if (!data->slot[0].bus_width)
418 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
420 struct at_dma_slave *atslave;
421 struct mci_dma_data *alt_atslave;
423 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
424 atslave = &alt_atslave->sdata;
426 /* DMA slave channel configuration */
427 atslave->dma_dev = &at_hdmac_device.dev;
428 atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
429 atslave->cfg = ATC_FIFOCFG_HALFFIFO
430 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
431 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
432 if (mmc_id == 0) /* MCI0 */
433 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
434 | ATC_DST_PER(AT_DMA_ID_MCI0);
437 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
438 | ATC_DST_PER(AT_DMA_ID_MCI1);
440 data->dma_slave = alt_atslave;
446 if (data->slot[0].detect_pin) {
447 at91_set_gpio_input(data->slot[0].detect_pin, 1);
448 at91_set_deglitch(data->slot[0].detect_pin, 1);
450 if (data->slot[0].wp_pin)
451 at91_set_gpio_input(data->slot[0].wp_pin, 1);
453 if (mmc_id == 0) { /* MCI0 */
456 at91_set_A_periph(AT91_PIN_PA0, 0);
459 at91_set_A_periph(AT91_PIN_PA1, 1);
461 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
462 at91_set_A_periph(AT91_PIN_PA2, 1);
463 if (data->slot[0].bus_width == 4) {
464 at91_set_A_periph(AT91_PIN_PA3, 1);
465 at91_set_A_periph(AT91_PIN_PA4, 1);
466 at91_set_A_periph(AT91_PIN_PA5, 1);
467 if (data->slot[0].bus_width == 8) {
468 at91_set_A_periph(AT91_PIN_PA6, 1);
469 at91_set_A_periph(AT91_PIN_PA7, 1);
470 at91_set_A_periph(AT91_PIN_PA8, 1);
471 at91_set_A_periph(AT91_PIN_PA9, 1);
476 platform_device_register(&at91sam9g45_mmc0_device);
481 at91_set_A_periph(AT91_PIN_PA31, 0);
484 at91_set_A_periph(AT91_PIN_PA22, 1);
486 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
487 at91_set_A_periph(AT91_PIN_PA23, 1);
488 if (data->slot[0].bus_width == 4) {
489 at91_set_A_periph(AT91_PIN_PA24, 1);
490 at91_set_A_periph(AT91_PIN_PA25, 1);
491 at91_set_A_periph(AT91_PIN_PA26, 1);
492 if (data->slot[0].bus_width == 8) {
493 at91_set_A_periph(AT91_PIN_PA27, 1);
494 at91_set_A_periph(AT91_PIN_PA28, 1);
495 at91_set_A_periph(AT91_PIN_PA29, 1);
496 at91_set_A_periph(AT91_PIN_PA30, 1);
501 platform_device_register(&at91sam9g45_mmc1_device);
506 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
510 /* --------------------------------------------------------------------
512 * -------------------------------------------------------------------- */
514 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
515 static struct atmel_nand_data nand_data;
517 #define NAND_BASE AT91_CHIPSELECT_3
519 static struct resource nand_resources[] = {
522 .end = NAND_BASE + SZ_256M - 1,
523 .flags = IORESOURCE_MEM,
526 .start = AT91_BASE_SYS + AT91_ECC,
527 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
528 .flags = IORESOURCE_MEM,
532 static struct platform_device at91sam9g45_nand_device = {
533 .name = "atmel_nand",
536 .platform_data = &nand_data,
538 .resource = nand_resources,
539 .num_resources = ARRAY_SIZE(nand_resources),
542 void __init at91_add_device_nand(struct atmel_nand_data *data)
549 csa = at91_sys_read(AT91_MATRIX_EBICSA);
550 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
553 if (data->enable_pin)
554 at91_set_gpio_output(data->enable_pin, 1);
558 at91_set_gpio_input(data->rdy_pin, 1);
560 /* card detect pin */
562 at91_set_gpio_input(data->det_pin, 1);
565 platform_device_register(&at91sam9g45_nand_device);
568 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
572 /* --------------------------------------------------------------------
574 * -------------------------------------------------------------------- */
577 * Prefer the GPIO code since the TWI controller isn't robust
578 * (gets overruns and underruns under load) and can only issue
579 * repeated STARTs in one scenario (the driver doesn't yet handle them).
581 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
582 static struct i2c_gpio_platform_data pdata_i2c0 = {
583 .sda_pin = AT91_PIN_PA20,
584 .sda_is_open_drain = 1,
585 .scl_pin = AT91_PIN_PA21,
586 .scl_is_open_drain = 1,
587 .udelay = 5, /* ~100 kHz */
590 static struct platform_device at91sam9g45_twi0_device = {
593 .dev.platform_data = &pdata_i2c0,
596 static struct i2c_gpio_platform_data pdata_i2c1 = {
597 .sda_pin = AT91_PIN_PB10,
598 .sda_is_open_drain = 1,
599 .scl_pin = AT91_PIN_PB11,
600 .scl_is_open_drain = 1,
601 .udelay = 5, /* ~100 kHz */
604 static struct platform_device at91sam9g45_twi1_device = {
607 .dev.platform_data = &pdata_i2c1,
610 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
612 i2c_register_board_info(i2c_id, devices, nr_devices);
615 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
616 at91_set_multi_drive(AT91_PIN_PA20, 1);
618 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
619 at91_set_multi_drive(AT91_PIN_PA21, 1);
621 platform_device_register(&at91sam9g45_twi0_device);
623 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
624 at91_set_multi_drive(AT91_PIN_PB10, 1);
626 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
627 at91_set_multi_drive(AT91_PIN_PB11, 1);
629 platform_device_register(&at91sam9g45_twi1_device);
633 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
634 static struct resource twi0_resources[] = {
636 .start = AT91SAM9G45_BASE_TWI0,
637 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
638 .flags = IORESOURCE_MEM,
641 .start = AT91SAM9G45_ID_TWI0,
642 .end = AT91SAM9G45_ID_TWI0,
643 .flags = IORESOURCE_IRQ,
647 static struct platform_device at91sam9g45_twi0_device = {
650 .resource = twi0_resources,
651 .num_resources = ARRAY_SIZE(twi0_resources),
654 static struct resource twi1_resources[] = {
656 .start = AT91SAM9G45_BASE_TWI1,
657 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
658 .flags = IORESOURCE_MEM,
661 .start = AT91SAM9G45_ID_TWI1,
662 .end = AT91SAM9G45_ID_TWI1,
663 .flags = IORESOURCE_IRQ,
667 static struct platform_device at91sam9g45_twi1_device = {
670 .resource = twi1_resources,
671 .num_resources = ARRAY_SIZE(twi1_resources),
674 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
676 i2c_register_board_info(i2c_id, devices, nr_devices);
678 /* pins used for TWI interface */
680 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
681 at91_set_multi_drive(AT91_PIN_PA20, 1);
683 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
684 at91_set_multi_drive(AT91_PIN_PA21, 1);
686 platform_device_register(&at91sam9g45_twi0_device);
688 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
689 at91_set_multi_drive(AT91_PIN_PB10, 1);
691 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
692 at91_set_multi_drive(AT91_PIN_PB11, 1);
694 platform_device_register(&at91sam9g45_twi1_device);
698 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
702 /* --------------------------------------------------------------------
704 * -------------------------------------------------------------------- */
706 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
707 static u64 spi_dmamask = DMA_BIT_MASK(32);
709 static struct resource spi0_resources[] = {
711 .start = AT91SAM9G45_BASE_SPI0,
712 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
713 .flags = IORESOURCE_MEM,
716 .start = AT91SAM9G45_ID_SPI0,
717 .end = AT91SAM9G45_ID_SPI0,
718 .flags = IORESOURCE_IRQ,
722 static struct platform_device at91sam9g45_spi0_device = {
726 .dma_mask = &spi_dmamask,
727 .coherent_dma_mask = DMA_BIT_MASK(32),
729 .resource = spi0_resources,
730 .num_resources = ARRAY_SIZE(spi0_resources),
733 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
735 static struct resource spi1_resources[] = {
737 .start = AT91SAM9G45_BASE_SPI1,
738 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
739 .flags = IORESOURCE_MEM,
742 .start = AT91SAM9G45_ID_SPI1,
743 .end = AT91SAM9G45_ID_SPI1,
744 .flags = IORESOURCE_IRQ,
748 static struct platform_device at91sam9g45_spi1_device = {
752 .dma_mask = &spi_dmamask,
753 .coherent_dma_mask = DMA_BIT_MASK(32),
755 .resource = spi1_resources,
756 .num_resources = ARRAY_SIZE(spi1_resources),
759 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
761 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
764 unsigned long cs_pin;
765 short enable_spi0 = 0;
766 short enable_spi1 = 0;
768 /* Choose SPI chip-selects */
769 for (i = 0; i < nr_devices; i++) {
770 if (devices[i].controller_data)
771 cs_pin = (unsigned long) devices[i].controller_data;
772 else if (devices[i].bus_num == 0)
773 cs_pin = spi0_standard_cs[devices[i].chip_select];
775 cs_pin = spi1_standard_cs[devices[i].chip_select];
777 if (devices[i].bus_num == 0)
782 /* enable chip-select pin */
783 at91_set_gpio_output(cs_pin, 1);
785 /* pass chip-select pin to driver */
786 devices[i].controller_data = (void *) cs_pin;
789 spi_register_board_info(devices, nr_devices);
791 /* Configure SPI bus(es) */
793 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
794 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
795 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
797 platform_device_register(&at91sam9g45_spi0_device);
800 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
801 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
802 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
804 platform_device_register(&at91sam9g45_spi1_device);
808 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
812 /* --------------------------------------------------------------------
814 * -------------------------------------------------------------------- */
816 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
817 static u64 ac97_dmamask = DMA_BIT_MASK(32);
818 static struct ac97c_platform_data ac97_data;
820 static struct resource ac97_resources[] = {
822 .start = AT91SAM9G45_BASE_AC97C,
823 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
824 .flags = IORESOURCE_MEM,
827 .start = AT91SAM9G45_ID_AC97C,
828 .end = AT91SAM9G45_ID_AC97C,
829 .flags = IORESOURCE_IRQ,
833 static struct platform_device at91sam9g45_ac97_device = {
834 .name = "atmel_ac97c",
837 .dma_mask = &ac97_dmamask,
838 .coherent_dma_mask = DMA_BIT_MASK(32),
839 .platform_data = &ac97_data,
841 .resource = ac97_resources,
842 .num_resources = ARRAY_SIZE(ac97_resources),
845 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
850 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
851 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
852 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
853 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
857 at91_set_gpio_output(data->reset_pin, 0);
860 platform_device_register(&at91sam9g45_ac97_device);
863 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
867 /* --------------------------------------------------------------------
869 * -------------------------------------------------------------------- */
871 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
872 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
873 static struct atmel_lcdfb_info lcdc_data;
875 static struct resource lcdc_resources[] = {
877 .start = AT91SAM9G45_LCDC_BASE,
878 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
879 .flags = IORESOURCE_MEM,
882 .start = AT91SAM9G45_ID_LCDC,
883 .end = AT91SAM9G45_ID_LCDC,
884 .flags = IORESOURCE_IRQ,
888 static struct platform_device at91_lcdc_device = {
889 .name = "atmel_lcdfb",
892 .dma_mask = &lcdc_dmamask,
893 .coherent_dma_mask = DMA_BIT_MASK(32),
894 .platform_data = &lcdc_data,
896 .resource = lcdc_resources,
897 .num_resources = ARRAY_SIZE(lcdc_resources),
900 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
905 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
907 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
908 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
909 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
910 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
911 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
912 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
913 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
914 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
915 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
916 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
917 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
918 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
919 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
920 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
921 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
922 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
923 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
924 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
925 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
926 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
927 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
928 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
929 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
930 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
931 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
932 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
933 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
934 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
935 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
938 platform_device_register(&at91_lcdc_device);
941 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
945 /* --------------------------------------------------------------------
946 * Timer/Counter block
947 * -------------------------------------------------------------------- */
949 #ifdef CONFIG_ATMEL_TCLIB
950 static struct resource tcb0_resources[] = {
952 .start = AT91SAM9G45_BASE_TCB0,
953 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
957 .start = AT91SAM9G45_ID_TCB,
958 .end = AT91SAM9G45_ID_TCB,
959 .flags = IORESOURCE_IRQ,
963 static struct platform_device at91sam9g45_tcb0_device = {
966 .resource = tcb0_resources,
967 .num_resources = ARRAY_SIZE(tcb0_resources),
970 /* TCB1 begins with TC3 */
971 static struct resource tcb1_resources[] = {
973 .start = AT91SAM9G45_BASE_TCB1,
974 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
975 .flags = IORESOURCE_MEM,
978 .start = AT91SAM9G45_ID_TCB,
979 .end = AT91SAM9G45_ID_TCB,
980 .flags = IORESOURCE_IRQ,
984 static struct platform_device at91sam9g45_tcb1_device = {
987 .resource = tcb1_resources,
988 .num_resources = ARRAY_SIZE(tcb1_resources),
991 static void __init at91_add_device_tc(void)
993 platform_device_register(&at91sam9g45_tcb0_device);
994 platform_device_register(&at91sam9g45_tcb1_device);
997 static void __init at91_add_device_tc(void) { }
1001 /* --------------------------------------------------------------------
1003 * -------------------------------------------------------------------- */
1005 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1006 static struct platform_device at91sam9g45_rtc_device = {
1012 static void __init at91_add_device_rtc(void)
1014 platform_device_register(&at91sam9g45_rtc_device);
1017 static void __init at91_add_device_rtc(void) {}
1021 /* --------------------------------------------------------------------
1023 * -------------------------------------------------------------------- */
1025 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1026 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1027 static struct at91_tsadcc_data tsadcc_data;
1029 static struct resource tsadcc_resources[] = {
1031 .start = AT91SAM9G45_BASE_TSC,
1032 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1033 .flags = IORESOURCE_MEM,
1036 .start = AT91SAM9G45_ID_TSC,
1037 .end = AT91SAM9G45_ID_TSC,
1038 .flags = IORESOURCE_IRQ,
1042 static struct platform_device at91sam9g45_tsadcc_device = {
1043 .name = "atmel_tsadcc",
1046 .dma_mask = &tsadcc_dmamask,
1047 .coherent_dma_mask = DMA_BIT_MASK(32),
1048 .platform_data = &tsadcc_data,
1050 .resource = tsadcc_resources,
1051 .num_resources = ARRAY_SIZE(tsadcc_resources),
1054 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1059 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1060 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1061 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1062 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1064 tsadcc_data = *data;
1065 platform_device_register(&at91sam9g45_tsadcc_device);
1068 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1072 /* --------------------------------------------------------------------
1074 * -------------------------------------------------------------------- */
1076 static struct resource rtt_resources[] = {
1078 .start = AT91_BASE_SYS + AT91_RTT,
1079 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
1080 .flags = IORESOURCE_MEM,
1084 static struct platform_device at91sam9g45_rtt_device = {
1087 .resource = rtt_resources,
1088 .num_resources = ARRAY_SIZE(rtt_resources),
1091 static void __init at91_add_device_rtt(void)
1093 platform_device_register(&at91sam9g45_rtt_device);
1097 /* --------------------------------------------------------------------
1099 * -------------------------------------------------------------------- */
1101 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1102 static struct resource trng_resources[] = {
1104 .start = AT91SAM9G45_BASE_TRNG,
1105 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1106 .flags = IORESOURCE_MEM,
1110 static struct platform_device at91sam9g45_trng_device = {
1111 .name = "atmel-trng",
1113 .resource = trng_resources,
1114 .num_resources = ARRAY_SIZE(trng_resources),
1117 static void __init at91_add_device_trng(void)
1119 platform_device_register(&at91sam9g45_trng_device);
1122 static void __init at91_add_device_trng(void) {}
1125 /* --------------------------------------------------------------------
1127 * -------------------------------------------------------------------- */
1129 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1130 static struct platform_device at91sam9g45_wdt_device = {
1136 static void __init at91_add_device_watchdog(void)
1138 platform_device_register(&at91sam9g45_wdt_device);
1141 static void __init at91_add_device_watchdog(void) {}
1145 /* --------------------------------------------------------------------
1147 * --------------------------------------------------------------------*/
1149 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1150 static u32 pwm_mask;
1152 static struct resource pwm_resources[] = {
1154 .start = AT91SAM9G45_BASE_PWMC,
1155 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1156 .flags = IORESOURCE_MEM,
1159 .start = AT91SAM9G45_ID_PWMC,
1160 .end = AT91SAM9G45_ID_PWMC,
1161 .flags = IORESOURCE_IRQ,
1165 static struct platform_device at91sam9g45_pwm0_device = {
1166 .name = "atmel_pwm",
1169 .platform_data = &pwm_mask,
1171 .resource = pwm_resources,
1172 .num_resources = ARRAY_SIZE(pwm_resources),
1175 void __init at91_add_device_pwm(u32 mask)
1177 if (mask & (1 << AT91_PWM0))
1178 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1180 if (mask & (1 << AT91_PWM1))
1181 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1183 if (mask & (1 << AT91_PWM2))
1184 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1186 if (mask & (1 << AT91_PWM3))
1187 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1191 platform_device_register(&at91sam9g45_pwm0_device);
1194 void __init at91_add_device_pwm(u32 mask) {}
1198 /* --------------------------------------------------------------------
1199 * SSC -- Synchronous Serial Controller
1200 * -------------------------------------------------------------------- */
1202 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1203 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1205 static struct resource ssc0_resources[] = {
1207 .start = AT91SAM9G45_BASE_SSC0,
1208 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1209 .flags = IORESOURCE_MEM,
1212 .start = AT91SAM9G45_ID_SSC0,
1213 .end = AT91SAM9G45_ID_SSC0,
1214 .flags = IORESOURCE_IRQ,
1218 static struct platform_device at91sam9g45_ssc0_device = {
1222 .dma_mask = &ssc0_dmamask,
1223 .coherent_dma_mask = DMA_BIT_MASK(32),
1225 .resource = ssc0_resources,
1226 .num_resources = ARRAY_SIZE(ssc0_resources),
1229 static inline void configure_ssc0_pins(unsigned pins)
1231 if (pins & ATMEL_SSC_TF)
1232 at91_set_A_periph(AT91_PIN_PD1, 1);
1233 if (pins & ATMEL_SSC_TK)
1234 at91_set_A_periph(AT91_PIN_PD0, 1);
1235 if (pins & ATMEL_SSC_TD)
1236 at91_set_A_periph(AT91_PIN_PD2, 1);
1237 if (pins & ATMEL_SSC_RD)
1238 at91_set_A_periph(AT91_PIN_PD3, 1);
1239 if (pins & ATMEL_SSC_RK)
1240 at91_set_A_periph(AT91_PIN_PD4, 1);
1241 if (pins & ATMEL_SSC_RF)
1242 at91_set_A_periph(AT91_PIN_PD5, 1);
1245 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1247 static struct resource ssc1_resources[] = {
1249 .start = AT91SAM9G45_BASE_SSC1,
1250 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1251 .flags = IORESOURCE_MEM,
1254 .start = AT91SAM9G45_ID_SSC1,
1255 .end = AT91SAM9G45_ID_SSC1,
1256 .flags = IORESOURCE_IRQ,
1260 static struct platform_device at91sam9g45_ssc1_device = {
1264 .dma_mask = &ssc1_dmamask,
1265 .coherent_dma_mask = DMA_BIT_MASK(32),
1267 .resource = ssc1_resources,
1268 .num_resources = ARRAY_SIZE(ssc1_resources),
1271 static inline void configure_ssc1_pins(unsigned pins)
1273 if (pins & ATMEL_SSC_TF)
1274 at91_set_A_periph(AT91_PIN_PD14, 1);
1275 if (pins & ATMEL_SSC_TK)
1276 at91_set_A_periph(AT91_PIN_PD12, 1);
1277 if (pins & ATMEL_SSC_TD)
1278 at91_set_A_periph(AT91_PIN_PD10, 1);
1279 if (pins & ATMEL_SSC_RD)
1280 at91_set_A_periph(AT91_PIN_PD11, 1);
1281 if (pins & ATMEL_SSC_RK)
1282 at91_set_A_periph(AT91_PIN_PD13, 1);
1283 if (pins & ATMEL_SSC_RF)
1284 at91_set_A_periph(AT91_PIN_PD15, 1);
1288 * SSC controllers are accessed through library code, instead of any
1289 * kind of all-singing/all-dancing driver. For example one could be
1290 * used by a particular I2S audio codec's driver, while another one
1291 * on the same system might be used by a custom data capture driver.
1293 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1295 struct platform_device *pdev;
1298 * NOTE: caller is responsible for passing information matching
1299 * "pins" to whatever will be using each particular controller.
1302 case AT91SAM9G45_ID_SSC0:
1303 pdev = &at91sam9g45_ssc0_device;
1304 configure_ssc0_pins(pins);
1306 case AT91SAM9G45_ID_SSC1:
1307 pdev = &at91sam9g45_ssc1_device;
1308 configure_ssc1_pins(pins);
1314 platform_device_register(pdev);
1318 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1322 /* --------------------------------------------------------------------
1324 * -------------------------------------------------------------------- */
1326 #if defined(CONFIG_SERIAL_ATMEL)
1327 static struct resource dbgu_resources[] = {
1329 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1330 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1331 .flags = IORESOURCE_MEM,
1334 .start = AT91_ID_SYS,
1336 .flags = IORESOURCE_IRQ,
1340 static struct atmel_uart_data dbgu_data = {
1343 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1346 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1348 static struct platform_device at91sam9g45_dbgu_device = {
1349 .name = "atmel_usart",
1352 .dma_mask = &dbgu_dmamask,
1353 .coherent_dma_mask = DMA_BIT_MASK(32),
1354 .platform_data = &dbgu_data,
1356 .resource = dbgu_resources,
1357 .num_resources = ARRAY_SIZE(dbgu_resources),
1360 static inline void configure_dbgu_pins(void)
1362 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1363 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1366 static struct resource uart0_resources[] = {
1368 .start = AT91SAM9G45_BASE_US0,
1369 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1370 .flags = IORESOURCE_MEM,
1373 .start = AT91SAM9G45_ID_US0,
1374 .end = AT91SAM9G45_ID_US0,
1375 .flags = IORESOURCE_IRQ,
1379 static struct atmel_uart_data uart0_data = {
1384 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1386 static struct platform_device at91sam9g45_uart0_device = {
1387 .name = "atmel_usart",
1390 .dma_mask = &uart0_dmamask,
1391 .coherent_dma_mask = DMA_BIT_MASK(32),
1392 .platform_data = &uart0_data,
1394 .resource = uart0_resources,
1395 .num_resources = ARRAY_SIZE(uart0_resources),
1398 static inline void configure_usart0_pins(unsigned pins)
1400 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1401 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1403 if (pins & ATMEL_UART_RTS)
1404 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1405 if (pins & ATMEL_UART_CTS)
1406 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1409 static struct resource uart1_resources[] = {
1411 .start = AT91SAM9G45_BASE_US1,
1412 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1413 .flags = IORESOURCE_MEM,
1416 .start = AT91SAM9G45_ID_US1,
1417 .end = AT91SAM9G45_ID_US1,
1418 .flags = IORESOURCE_IRQ,
1422 static struct atmel_uart_data uart1_data = {
1427 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1429 static struct platform_device at91sam9g45_uart1_device = {
1430 .name = "atmel_usart",
1433 .dma_mask = &uart1_dmamask,
1434 .coherent_dma_mask = DMA_BIT_MASK(32),
1435 .platform_data = &uart1_data,
1437 .resource = uart1_resources,
1438 .num_resources = ARRAY_SIZE(uart1_resources),
1441 static inline void configure_usart1_pins(unsigned pins)
1443 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1444 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1446 if (pins & ATMEL_UART_RTS)
1447 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1448 if (pins & ATMEL_UART_CTS)
1449 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1452 static struct resource uart2_resources[] = {
1454 .start = AT91SAM9G45_BASE_US2,
1455 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1456 .flags = IORESOURCE_MEM,
1459 .start = AT91SAM9G45_ID_US2,
1460 .end = AT91SAM9G45_ID_US2,
1461 .flags = IORESOURCE_IRQ,
1465 static struct atmel_uart_data uart2_data = {
1470 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1472 static struct platform_device at91sam9g45_uart2_device = {
1473 .name = "atmel_usart",
1476 .dma_mask = &uart2_dmamask,
1477 .coherent_dma_mask = DMA_BIT_MASK(32),
1478 .platform_data = &uart2_data,
1480 .resource = uart2_resources,
1481 .num_resources = ARRAY_SIZE(uart2_resources),
1484 static inline void configure_usart2_pins(unsigned pins)
1486 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1487 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1489 if (pins & ATMEL_UART_RTS)
1490 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1491 if (pins & ATMEL_UART_CTS)
1492 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1495 static struct resource uart3_resources[] = {
1497 .start = AT91SAM9G45_BASE_US3,
1498 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1499 .flags = IORESOURCE_MEM,
1502 .start = AT91SAM9G45_ID_US3,
1503 .end = AT91SAM9G45_ID_US3,
1504 .flags = IORESOURCE_IRQ,
1508 static struct atmel_uart_data uart3_data = {
1513 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1515 static struct platform_device at91sam9g45_uart3_device = {
1516 .name = "atmel_usart",
1519 .dma_mask = &uart3_dmamask,
1520 .coherent_dma_mask = DMA_BIT_MASK(32),
1521 .platform_data = &uart3_data,
1523 .resource = uart3_resources,
1524 .num_resources = ARRAY_SIZE(uart3_resources),
1527 static inline void configure_usart3_pins(unsigned pins)
1529 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1530 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1532 if (pins & ATMEL_UART_RTS)
1533 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1534 if (pins & ATMEL_UART_CTS)
1535 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1538 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1539 struct platform_device *atmel_default_console_device; /* the serial console device */
1541 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1543 struct platform_device *pdev;
1544 struct atmel_uart_data *pdata;
1548 pdev = &at91sam9g45_dbgu_device;
1549 configure_dbgu_pins();
1551 case AT91SAM9G45_ID_US0:
1552 pdev = &at91sam9g45_uart0_device;
1553 configure_usart0_pins(pins);
1555 case AT91SAM9G45_ID_US1:
1556 pdev = &at91sam9g45_uart1_device;
1557 configure_usart1_pins(pins);
1559 case AT91SAM9G45_ID_US2:
1560 pdev = &at91sam9g45_uart2_device;
1561 configure_usart2_pins(pins);
1563 case AT91SAM9G45_ID_US3:
1564 pdev = &at91sam9g45_uart3_device;
1565 configure_usart3_pins(pins);
1570 pdata = pdev->dev.platform_data;
1571 pdata->num = portnr; /* update to mapped ID */
1573 if (portnr < ATMEL_MAX_UART)
1574 at91_uarts[portnr] = pdev;
1577 void __init at91_set_serial_console(unsigned portnr)
1579 if (portnr < ATMEL_MAX_UART) {
1580 atmel_default_console_device = at91_uarts[portnr];
1581 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1585 void __init at91_add_device_serial(void)
1589 for (i = 0; i < ATMEL_MAX_UART; i++) {
1591 platform_device_register(at91_uarts[i]);
1594 if (!atmel_default_console_device)
1595 printk(KERN_INFO "AT91: No default serial console defined.\n");
1598 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1599 void __init at91_set_serial_console(unsigned portnr) {}
1600 void __init at91_add_device_serial(void) {}
1604 /* -------------------------------------------------------------------- */
1606 * These devices are always present and don't need any board-specific
1609 static int __init at91_add_standard_devices(void)
1611 at91_add_device_hdmac();
1612 at91_add_device_rtc();
1613 at91_add_device_rtt();
1614 at91_add_device_trng();
1615 at91_add_device_watchdog();
1616 at91_add_device_tc();
1620 arch_initcall(at91_add_standard_devices);