2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_pmc.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk = {
39 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
42 static struct clk pioB_clk = {
44 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
47 static struct clk pioC_clk = {
49 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk pioDE_clk = {
54 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk trng_clk = {
59 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
60 .type = CLK_TYPE_PERIPHERAL,
62 static struct clk usart0_clk = {
64 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
65 .type = CLK_TYPE_PERIPHERAL,
67 static struct clk usart1_clk = {
69 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
70 .type = CLK_TYPE_PERIPHERAL,
72 static struct clk usart2_clk = {
74 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
75 .type = CLK_TYPE_PERIPHERAL,
77 static struct clk usart3_clk = {
79 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
80 .type = CLK_TYPE_PERIPHERAL,
82 static struct clk mmc0_clk = {
84 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
85 .type = CLK_TYPE_PERIPHERAL,
87 static struct clk twi0_clk = {
89 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
90 .type = CLK_TYPE_PERIPHERAL,
92 static struct clk twi1_clk = {
94 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
95 .type = CLK_TYPE_PERIPHERAL,
97 static struct clk spi0_clk = {
99 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
100 .type = CLK_TYPE_PERIPHERAL,
102 static struct clk spi1_clk = {
104 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
105 .type = CLK_TYPE_PERIPHERAL,
107 static struct clk ssc0_clk = {
109 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
110 .type = CLK_TYPE_PERIPHERAL,
112 static struct clk ssc1_clk = {
114 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
115 .type = CLK_TYPE_PERIPHERAL,
117 static struct clk tcb0_clk = {
119 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
120 .type = CLK_TYPE_PERIPHERAL,
122 static struct clk pwm_clk = {
124 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
125 .type = CLK_TYPE_PERIPHERAL,
127 static struct clk tsc_clk = {
129 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
130 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk dma_clk = {
134 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
135 .type = CLK_TYPE_PERIPHERAL,
137 static struct clk uhphs_clk = {
139 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
140 .type = CLK_TYPE_PERIPHERAL,
142 static struct clk lcdc_clk = {
144 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
145 .type = CLK_TYPE_PERIPHERAL,
147 static struct clk ac97_clk = {
149 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
150 .type = CLK_TYPE_PERIPHERAL,
152 static struct clk macb_clk = {
154 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
155 .type = CLK_TYPE_PERIPHERAL,
157 static struct clk isi_clk = {
159 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
160 .type = CLK_TYPE_PERIPHERAL,
162 static struct clk udphs_clk = {
164 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
165 .type = CLK_TYPE_PERIPHERAL,
167 static struct clk mmc1_clk = {
169 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
170 .type = CLK_TYPE_PERIPHERAL,
173 /* Video decoder clock - Only for sam9m10/sam9m11 */
174 static struct clk vdec_clk = {
176 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
177 .type = CLK_TYPE_PERIPHERAL,
180 static struct clk adc_op_clk = {
181 .name = "adc_op_clk",
182 .type = CLK_TYPE_PERIPHERAL,
186 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
187 static struct clk aestdessha_clk = {
188 .name = "aestdessha_clk",
189 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
190 .type = CLK_TYPE_PERIPHERAL,
193 static struct clk *periph_clocks[] __initdata = {
226 static struct clk_lookup periph_clocks_lookups[] = {
227 /* One additional fake clock for macb_hclk */
228 CLKDEV_CON_ID("hclk", &macb_clk),
229 /* One additional fake clock for ohci */
230 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
231 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
232 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
233 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
234 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
235 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
236 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
237 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
238 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
239 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
240 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
241 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
242 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
243 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
244 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
245 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
246 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
247 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
248 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
249 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
250 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
251 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
252 /* more usart lookup table for DT entries */
253 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
254 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
255 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
256 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
257 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
258 /* more tc lookup table for DT entries */
259 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
260 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
261 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
262 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
263 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
264 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
265 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
266 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
267 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
268 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
269 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
270 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
271 /* fake hclk clock */
272 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
273 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
274 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
275 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
276 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
277 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
279 CLKDEV_CON_ID("pioA", &pioA_clk),
280 CLKDEV_CON_ID("pioB", &pioB_clk),
281 CLKDEV_CON_ID("pioC", &pioC_clk),
282 CLKDEV_CON_ID("pioD", &pioDE_clk),
283 CLKDEV_CON_ID("pioE", &pioDE_clk),
285 CLKDEV_CON_ID("adc_clk", &tsc_clk),
288 static struct clk_lookup usart_clocks_lookups[] = {
289 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
290 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
291 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
292 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
293 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
297 * The two programmable clocks.
298 * You must configure pin multiplexing to bring these signals out.
300 static struct clk pck0 = {
302 .pmc_mask = AT91_PMC_PCK0,
303 .type = CLK_TYPE_PROGRAMMABLE,
306 static struct clk pck1 = {
308 .pmc_mask = AT91_PMC_PCK1,
309 .type = CLK_TYPE_PROGRAMMABLE,
313 static void __init at91sam9g45_register_clocks(void)
317 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
318 clk_register(periph_clocks[i]);
320 clkdev_add_table(periph_clocks_lookups,
321 ARRAY_SIZE(periph_clocks_lookups));
322 clkdev_add_table(usart_clocks_lookups,
323 ARRAY_SIZE(usart_clocks_lookups));
325 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
326 clk_register(&vdec_clk);
332 /* --------------------------------------------------------------------
334 * -------------------------------------------------------------------- */
336 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
338 .id = AT91SAM9G45_ID_PIOA,
339 .regbase = AT91SAM9G45_BASE_PIOA,
341 .id = AT91SAM9G45_ID_PIOB,
342 .regbase = AT91SAM9G45_BASE_PIOB,
344 .id = AT91SAM9G45_ID_PIOC,
345 .regbase = AT91SAM9G45_BASE_PIOC,
347 .id = AT91SAM9G45_ID_PIODE,
348 .regbase = AT91SAM9G45_BASE_PIOD,
350 .id = AT91SAM9G45_ID_PIODE,
351 .regbase = AT91SAM9G45_BASE_PIOE,
355 /* --------------------------------------------------------------------
356 * AT91SAM9G45 processor initialization
357 * -------------------------------------------------------------------- */
359 static void __init at91sam9g45_map_io(void)
361 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
364 static void __init at91sam9g45_ioremap_registers(void)
366 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
367 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
368 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
369 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
370 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
371 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
372 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
375 static void __init at91sam9g45_initialize(void)
377 arm_pm_idle = at91sam9_idle;
378 arm_pm_restart = at91sam9g45_restart;
380 /* Register GPIO subsystem */
381 at91_gpio_init(at91sam9g45_gpio, 5);
384 /* --------------------------------------------------------------------
385 * Interrupt initialization
386 * -------------------------------------------------------------------- */
389 * The default interrupt priority levels (0 = lowest, 7 = highest).
391 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
392 7, /* Advanced Interrupt Controller (FIQ) */
393 7, /* System Peripherals */
394 1, /* Parallel IO Controller A */
395 1, /* Parallel IO Controller B */
396 1, /* Parallel IO Controller C */
397 1, /* Parallel IO Controller D and E */
403 0, /* Multimedia Card Interface 0 */
404 6, /* Two-Wire Interface 0 */
405 6, /* Two-Wire Interface 1 */
406 5, /* Serial Peripheral Interface 0 */
407 5, /* Serial Peripheral Interface 1 */
408 4, /* Serial Synchronous Controller 0 */
409 4, /* Serial Synchronous Controller 1 */
410 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
411 0, /* Pulse Width Modulation Controller */
412 0, /* Touch Screen Controller */
413 0, /* DMA Controller */
414 2, /* USB Host High Speed port */
415 3, /* LDC Controller */
416 5, /* AC97 Controller */
418 0, /* Image Sensor Interface */
419 2, /* USB Device High speed port */
420 0, /* AESTDESSHA Crypto HW Accelerators */
421 0, /* Multimedia Card Interface 1 */
423 0, /* Advanced Interrupt Controller (IRQ0) */
426 AT91_SOC_START(at91sam9g45)
427 .map_io = at91sam9g45_map_io,
428 .default_irq_priority = at91sam9g45_default_irq_priority,
429 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
430 .ioremap_registers = at91sam9g45_ioremap_registers,
431 .register_clocks = at91sam9g45_register_clocks,
432 .init = at91sam9g45_initialize,